参数资料
型号: MCF5275CVM133
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 133 MHz, RISC PROCESSOR, PBGA256
封装: MAPBGA-256
文件页数: 16/44页
文件大小: 1242K
代理商: MCF5275CVM133
Preliminary Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
23
8.6
External Interface Timing Characteristics
Table 12 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11
tskew
-1
1
ns
Duty Cycle of reference 5
tdc
40
60
% fsys/2
Frequency un-LOCK Range
fUL
-3.8
4.1
% fsys/2
Frequency LOCK Range
fLCK
-1.7
2.0
% fsys/2
CLKOUT Period Jitter, 5, 6, 9,12, 13 Measured at fsys/2 Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
Cjitter
5
.01
% fsys/2
Frequency Modulation Range Limit14, 15
(fsys/2Max must not be exceeded)
Cmod
0.8
2.2
% fsys/2
ICO Frequency. fico = fref * 2 * (MFD+2)
16
fico
48
83
MHz
1
All values given are initial design targets and subject to change.
2
All internal registers retain data at 0 Hz.
3
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
4
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
fLOR with default MFD/RFD settings.
5
This parameter is guaranteed by characterization before qualification rather than 100% tested.
6
Proper PC board layout procedures must be followed to achieve specifications.
7
Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.
8
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
9
Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to
RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
10 t
lpll = (64 * 4 * 5 + 5 x τ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10
-6 x 2(MFD + 2)
11 PLL is operating in 1:1 PLL mode.
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the jitter percentage for a given interval.
13 Based on slow system clock of 33MHz maximum frequency.
14 Modulation percentage applies over an interval of 10
s, or equivalently the modulation rate is 100KHz.
15 Modulation rate selected must not result in f
sys/2 value greater than the fsys/2 maximum specified value. Modulation
range determined by hardware design.
16 f
sys/2 = fico / (2 * 2
RFD)
Table 11. PLL Electrical Specifications1 (continued)
Characteristic
Symbol
Min
Max
Unit
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