参数资料
型号: MCM63F737TQ9
厂商: MOTOROLA INC
元件分类: SRAM
英文描述: 128K X 36 CACHE SRAM, 9 ns, PQFP100
封装: TQFP-100
文件页数: 5/21页
文件大小: 320K
代理商: MCM63F737TQ9
MCM63F737
MCM63F819
13
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
1.0 V/ns (20% to 80%)
. . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
See Figure 2 Unless Otherwise Noted
. . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
P
Sb l
MCM63F737–8.5
MCM63F819–8.5
90 MHz
MCM63F737–9
MCM63F819–9
75 MHz
MCM63F737–10
MCM63F819–10
66 MHz
Ui
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
11
13.3
15
ns
Clock High Pulse Width
tKHKL
4.5
5.3
6
ns
Clock Low Pulse Width
tKLKH
4.5
5.3
6
ns
Clock Access Time
tKHQV
8.5
9
10
ns
Output Enable to Output Valid
tGLQV
3.5
3.5
3.5
ns
Clock High to Output Active
tKHQX1
0
0
0
ns
3, 4, 5
Clock High to Output Change
tKHQX2
2
2
2
ns
3, 4
Output Enable to Output Active
tGLQX
0
0
0
ns
3, 4
Output Disable to Q High–Z
tGHQZ
3.5
3.5
3.5
ns
3, 4
Clock High to Q High–Z
tKHQZ
2
3.5
2
3.5
2
3.5
ns
3, 4, 5
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
2.0
2.0
2.0
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
0.5
0.5
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. Measured at
± 200 mV from steady state.
4. This parameter is sampled and not 100% tested.
5. At any given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.
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