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| 型号： | MCP23S09T-E/MG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8 I/O, PIA-GENERAL PURPOSE, PQCC16 |
| 封装： | 3 X 3 MM, 0.90 MM HEIGHT, PLASTIC, QFN-16 |
| 文件页数： | 47/50页 |
| 文件大小： | 607K |
| 代理商： | MCP23S09T-E/MG |
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MCP23009/MCP23S09
DS22121B-page 6
2009 Microchip Technology Inc.
1.2
Power-on Reset (POR)
The on-chip POR circuit holds the device in reset until
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in the
electrical specification section.
When the device exits the POR condition (releases
reset), device operating parameters (i.e., voltage,
temperature, serial bus frequency, etc.) must be met to
ensure proper operation.
1.3
Serial Interface
This block handles the functionality of the I2C
(MCP23009) or SPI (MCP23S09) interface protocol.
The
MCP23X09
contains
eleven
(11)
individual
registers which can be addressed through the Serial
Interface block (Table 1-3).
TABLE 1-3:
REGISTER ADDRESSES
1.3.1
BYTE MODE AND SEQUENTIAL
MODE
The MCP23X09 has the ability to operate in “Byte
Mode” or “Sequential Mode” (IOCON.SEQOP). Byte
mode and sequential mode are not to be confused with
I2C byte operations and sequential operations. The
modes explained here relate to the device’s internal
address pointer and whether or not it is incremented
after each byte is clocked on the serial interface.
Byte Mode disables automatic address pointer incre-
menting.
When
operating
in
Byte
Mode,
the
MCP23X09 does not increment its internal address
counter after each byte during the data transfer. This
gives the ability to continually access the same address
by providing extra clocks (without additional control
bytes). This is useful for polling the GPIO register for
data changes or for continually writing to the output
latches.
Sequential Mode enables automatic address pointer
incrementing. When operating in Sequential Mode, the
MCP23X09 increments its address counter after each
byte during the data transfer. The address pointer
automatically rolls over to address 00h after accessing
the last register.
These two modes are not to be confused with single
writes/reads and continuous writes/reads which are
serial protocol sequences. For example, the device
may be configured for Byte Mode and the master may
perform
a
continuous
read.
In
this
case,
the
MCP23X09 would not increment the address pointer
and would repeatedly drive data from the same
location.
1.3.2
I2C INTERFACE
1.3.2.1
I2C Write Operation
The I2C write operation includes the control byte and
register address sequence, as shown in the bottom of
Figure 1-1. This sequence is followed by eight bits of
data from the master and an Acknowledge (ACK) from
the MCP23009. The operation is ended with a stop (P)
or restart (SR) condition being generated by the
master.
Data is written to the MCP23009 after every byte
transfer. If a stop or restart condition is generated
during a data transfer, the data will not be written to the
MCP23009.
Both “byte mode” and “sequential mode” are supported
by the MCP23009. If sequential mode is enabled
(default), the MCP23009 increments its address
counter after each ACK during the data transfer.
1.3.2.2
I2C Read Operation
I2C read operations include the control byte sequence,
as shown in the bottom of Figure 1-1. This sequence is
followed by another control byte (including the Start
condition and ACK) with the R/W bit equal to a logic
one (R/W = 1). The MCP23009 then transmits the data
contained in the addressed register. The sequence is
ended with the master generating a Stop or Restart
condition.
1.3.2.3
I2C Sequential Write/Read
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 1.3.1 “Byte Mode
and Sequential Mode” for details regarding sequential
operation control).
The sequence ends with the master sending a Stop or
Restart condition.
The MCP23009 address pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.
Address
Access to:
00h
IODIR
01h
IPOL
02h
GPINTEN
03h
DEFVAL
04h
INTCON
05h
IOCON
06h
GPPU
07h
INTF
08h
INTCAP (Read-only)
09h
GPIO
0Ah
OLAT
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