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| 型号： | MCP6566RT-E/OT |
| 厂商： | Microchip Technology |
| 文件页数： | 21/30页 |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR O-D 1.8V SOT23-5 |
| 产品培训模块： | MCP656x |
| 标准包装： | 1 |
| 类型： | 通用 |
| 元件数： | 1 |
| 输出类型： | CMOS，开路漏极 |
| 电压 - 电源，单路/双路(±)： | 1.8 V ~ 5.5 V |
| 电压 - 输入偏移（最小值）： | 10mV @ 5.5V |
| 电流 - 输入偏压（最小值）： | 1pA @ 5.5V |
| 电流 - 输出（标准）： | 50mA |
| 电流 - 静态（最大值）： | 130µA |
| CMRR, PSRR（标准）： | 66dB CMRR，70dB PSRR |
| 传输延迟（最大）： | 80ns |
| 磁滞： | 5mV |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | SC-74A，SOT-753 |
| 安装类型： | 表面贴装 |
| 包装： | 标准包装 |
| 产品目录页面： | 681 (CN2011-ZH PDF) |
| 其它名称： | MCP6566RT-E/OTDKR |
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36
DS580F6
CS8406
16.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER
MANAGEMENT
The CS8406 has a comprehensive channel status (C) and user (U) data buffering scheme which allows the user to
manage the C and U data through the control port.
16.1 AES3 Channel Status(C) Bit Management
The CS8406 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384
bits), and also 384 bits of U information. The user may read from or write to these RAM buffers through the
control port.
The CS8406 manages the flow of channel status data at the block level, meaning that entire blocks of chan-
nel status information are buffered at the input, synchronized to the output timebase, and then transmitted.
The buffering scheme involves a cascade of 2 block-sized buffers, named E and F, as shown in Figure 17.
The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0
(which is at control port address 20h) is the consumer/professional bit for channel status block A.
The E buffer is accessible from the control port, allowing read and writing of the C data. The F buffer is used
as the source of C data for the AES3 transmitter. The F buffer accepts block transfers from the E buffer.
16.1.1
Accessing the E buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register
space of the CS8406, through the control port. The user can modify the data to be transmitted by writing
to the E buffer.
The user can configure the interrupt enable register to cause interrupts to occur whenever “E to F” buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is an “E to F” inhibit bit. The “E to F” buffer transfer is disabled whenever the user sets this
bit. This may be used whenever “long” control port interactions are occurring.
A flowchart for reading and writing to the E buffer is shown in Figure 18. For writing, the sequence starts
after a E to F transfer, which is based on the output timebase.
If the channel status block to transmit indicates PRO Mode, then the CRCC byte is automatically calcu-
lated by the CS8406, and does not have to be written into the last byte of the block by the host microcon-
Control Port
To
AES3
Transm itter
E
24
words
8-bits
AB
F
Transm it
Data
Buffer
Figure 17. Channel Status Data Buffer Structure
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| MCP6566T-E/MC | 功能描述:校验器 IC SNGL 16V Open Drain Comparator E temp RoHS:否 制造商:STMicroelectronics 产品: 比较器类型: 通道数量: 输出类型:Push-Pull 电源电压-最大:5.5 V 电源电压-最小:1.1 V 补偿电压（最大值）:6 mV 电源电流（最大值）:1350 nA 响应时间: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SC-70-5 封装:Reel |
| MCP6566T-E/MS | 功能描述:校验器 IC SNGL 16V Open Drain Comparator E temp RoHS:否 制造商:STMicroelectronics 产品: 比较器类型: 通道数量: 输出类型:Push-Pull 电源电压-最大:5.5 V 电源电压-最小:1.1 V 补偿电压（最大值）:6 mV 电源电流（最大值）:1350 nA 响应时间: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SC-70-5 封装:Reel |
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