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参数资料
| 型号： | MCV18E-I/P |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP18 |
| 封装： | 0.300 INCH, LEAD FREE, PLASTIC, DIP-18 |
| 文件页数： | 66/108页 |
| 文件大小： | 1509K |
| 代理商： | MCV18E-I/P |
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MCV18E
DS41399A-page 60
2009 Microchip Technology Inc.
8.3.8
ENHANCED PWM AUTO-
SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
ECCPASx bits of the ECCPAS register. A shutdown
event may be generated by:
A logic ‘0’ on the INT pin
Setting the ECCPASE bit in firmware
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state. Refer to Figure 8-5.
When a shutdown event occurs, two things happen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 8.3.9 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSAC and
PSSBD bits of the ECCPAS register. Each pin pair may
be placed into one of three states:
Drive logic ‘1’
Drive logic ‘0’
Tri-state (high-impedance)
FIGURE 8-5:
AUTO-SHUTDOWN BLOCK DIAGRAM
PSSAC<1>
TRISx
P1A
0
1
P1A_DRV
PSSAC<0>
PSSBD<1>
TRISx
P1B
0
1
PSSBD<0>
P1B_DRV
PSSAC<1>
TRISx
P1C
0
1
PSSAC<0>
P1C_DRV
PSSBD<1>
TRISx
P1D
0
1
PSSBD<0>
P1D_DRV
000
001
010
011
100
101
110
111
From Comparator C2
From Comparator C1
ECCPAS<2:0>
R
DQ
S
ECCPASE
From Data Bus
Write to ECCPASE
PRSEN
INT
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