参数资料
型号: MCZ33291LEG
厂商: Freescale Semiconductor
文件页数: 8/26页
文件大小: 0K
描述: IC SWITCH 8X LOSIDE W/SPI 24SOIC
标准包装: 30
类型: 低端
输入类型: SPI
输出数: 8
导通状态电阻: 1.1 欧姆
电流 - 输出 / 通道: 500mA
电流 - 峰值输出: 3A
电源电压: 9 V ~ 26.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 管件
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ V DD ≤ 5.5 V, 9.0 V ≤ V PWR ≤ 16 V, -40 ° C ≤ T A ≤ 125 ° C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T A = 25 ° C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (V PWR = 13 V, R L = 26 Ω ) (26)
t r
0.4
5.0
20
μ s
Output Fall Time (V PWR = 13 V, R L = 26 Ω )
(26)
t f
0.4
5.0
20
μ s
Output Turn-ON Delay Time (V PWR = 13 V, R L = 26 Ω )
(27)
t dly (on)
1.0
15
50
μ s
Output Turn-OFF Delay Time (V PWR = 13 V, R L = 26 Ω )
(28)
t dly (off)
1.0
15
50
μ s
Output Short Fault Disable Report Delay
(29)
t dly (sf)
μ s
SFPD = 0.2 x V DD
70
150
250
Output OFF Fault Report Delay
(30)
t dly (off)
μ s
SFPD = 0.2 x V DD
70
150
250
DIGITAL INTERFACE TIMING
Required Low State Duration for RST (V IL < 0.2 V DD ) (31)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
SI to Falling Edge of SCLK (Required for Setup Time)
Falling Edge of SCLK to SI (Required for Hold Time)
SO Rise Time (C L = 200 pF)
SO Fall Time (C L = 200 pF)
t w(RST)
t lead
t lag
t SI (su)
t SI (hold)
t r (SO)
t f (SO)
50
50
50
25
25
25
25
167
167
167
83
83
50
50
ns
ns
ns
ns
ns
ns
ns
SI, CS , SCLK, Incoming Signal Rise Time
(32)
t r (SI)
50
ns
SI, CS , SCLK, Incoming Signal Fall Time
(32)
t f (SI)
50
ns
Time from Falling Edge of CS to SO Low-impedance
Time from Rising Edge of CS to SO High-impedance
(33)
(34)
t SO(en)
t SO(dis)
110
110
ns
ns
Time from Rising Edge of SCLK to SO Data Valid
(35)
t valid
ns
0.2 V DD ≤ SO ≥ 0.8 V DD , C L = 200 pF
65
105
Notes
26. Output Rise and Fall time respectively measured across a 26 Ω resistive load at 10% to 90% and 90% to 10% voltage points.
27. Output Turn-ON Delay time measured from 50% rising edge of CS to 90% of Output OFF voltage (V PWR ) with R L = 26 Ω resistive load.
28.
29.
30.
31.
32.
33.
34.
35.
Output Turn-OFF Delay time measured from 50% rising edge of CS to 10% of Output OFF voltage (V PWR ) with R L = 26 Ω resistive load.
Propagation time of Short Fault Disable Report measured from 50% rising edge of CS to 10% Output OFF voltage (V PWR ), V PWR =
6.0 V and SFPD = 2.0 x V DD .
Output OFF Fault Report Delay measured from 50% rising edge of CS to 10% rising edge of Output OFF voltage (V PWR ).
RST Low duration measured with outputs enabled and going to OFF or disabled condition.
Rise and Fall time of incoming SI, CS , and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at the SO pin.
Time required for output status data to be terminated at the SO pin.
Time required to obtain valid data out from SO following the rise of SCLK. See Figure 6 , page 9 .
33291L
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
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