参数资料
型号: MCZ33889BEGR2
厂商: Freescale Semiconductor
文件页数: 12/59页
文件大小: 0K
描述: IC SYSTEM BASIS W/CAN 28-SOIC
标准包装: 1,000
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 带卷 (TR)
安装类型: 表面贴装
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
33889
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations Between the 33889D and 33889B Versions (1)
Parameters
Symbol
Trait
Device Part Number
MC33889D(2)
Differential Receiver, Recessive To Dominant Threshold
(By Definition, VDIFF = VCANH-VCANL)
VDIFF1
Min
3.2 V
3.5 V
Typ
2.6 V
3.0 V
Max
2.1 V
2.5 V
Differential Receiver, Dominant To Recessive Threshold
(Bus Failures 1, 2, 5)
VDIFF2
Min
3.2 V
3.5 V
Typ
2.6 V
3.0 V
Max
2.1 V
2.5 V
CANH Output Current (VCANH = 0; TX = 0.0)
ICANH
Min
50 mA
Typ
75 mA
100 mA
Max
110 mA
130 mA
CANL Output Current (VCANL = 14 V; TX = 0.0)
ICANL
Min
50 mA
Typ
90 mA
140 mA
Max
135 mA
170 mA
Detection threshold for Short circuit to Battery voltage
Vcanh
max
Vsup/2 + 5V
Vsup/2 + 4.55V
loop time Tx to Rx, no bus failure, ISO configuration
tLOOPRD
max
N/A
1.5us
loop time Tx to Rx, with bus failure, ISO configuration
tLOOPRD-F
max
N/A
1.9us
loop time Tx to Rx, with bus failure and +-1.5V gnd shift,
5 node network, ISO configuration
tLOOPRD/DR-F+GS
N/A
3.6us
Minimum Dominant time for Wake up on CANL or CANH
(Tem Vbat mode)
tWAKE
min
N/A
8
typ
30
16
max
N/A
30
T2SPI timing
T2spi
min
not specified, 25us
spec applied
25us
DEVICE BEHAVIOR
CANH or CANL open wire recovery principle
after 4 non
consecutive pulses
after 4 consecutive
pulses
Rx behavior in TermVbat mode
Rx recessive, no pulse Rx recessive, dominant
pulse to signal bus
traffic
Notes
1.
This datasheet uses the term 33889 in the inclusive sense, referring to both the D version (33889D) and the B version (33689B).
2.
The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated
onto individual lines.
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