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参数资料
| 型号： | MCZ34701EWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 23/39页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY 1.5A SW 32-SOIC |
| 标准包装： | 1,000 |
| 应用： | 控制器，电源 QUICC? I、II |
| 输入电压： | 2.8 V ~ 6 V |
| 输出数： | 2 |
| 输出电压： | 7.75V，0.8 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 32-SOIC |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
5.0 V Input
34701
5.0 V Input
34701
VIN2
VBD
VBST
VIN1
LDRV
CS
VIN2
VBD
VBST
VIN1
LDRV
CS
RT
LDO
3.3 V
VDDH (I/Os)
RT
LDO
1.5 V
VDDL (Core)
ADDR
SDA
SCL
GND
LFB
RST
MCU
ADDR
SDA
SCL
GND
LFB
RST
MCU
5.0 V
EN1
EN2
BOOT
SW
VBST
1.5 V
VDDL (Core)
5.0 V
EN1
EN2
BOOT
SW
VBST
3.3 V
VDDH (I/Os)
CLKSYN
CLKSEL
VOUT
PGND
CLKSYN
CLKSEL
VOUT
PGND
Optional
FREQ
INV
Optional
FREQ
INV
VDDI
VDDI
? V = 2.1 V
Max. Lead
1.8V Start-Up
5.0 V Input Supply
3.3 V I/O Voltage (VLDO)
1.5 V Core Voltage
(VOUT)
? V = 2.1 V
Max. Lead
? V = 2.1 V
Max. Lead
1.8V Start-Up
5.0 V Input Supply
3.3 V I/O Voltage (VOUT)
1.5 V Core Voltage (VLDO)
? V = 0.4 V
? V = 0.4 V
Max. Lag
Max. Lag
? V = 2.1 V
Max. Lead
? V = 0.4 V
Max. Lag
? V = 0.4 V
Max. Lag
Figure 19. Inverted Power-up / Down Sequence in +5.0V
Figure 18. Standard Power-up / Down Sequence
in +5.0V Supply System
STANDARD POWER SEQUENCING
When the power supply IC operates in the Standard Power
Sequencing Mode, the switcher output provides the core
voltage for the microprocessor. This situation and operating
INVERTED POWER SEQUENCING
When the power supply IC is operating in the Inverted
Power Sequencing Mode, the linear regulator (LDO) output
provides the core voltage for the microprocessor, as
illustrated in Figure 19 . Table 5 shows the Power
Sequencing Mode selection.
Supply System
ASSUMED REQUIREMENTS
1. I/O supply voltage not to exceed core voltage by more
than 2.0V.
2. Core supply voltage not to exceed I/O voltage by more
than 0.4V.
Methods of Control
The 34701 has several methods of monitoring and
controlling the regulator output voltages, as described in the
paragraphs below. Power sequencing control is also
achieved through the intrinsic operation of the regulators.
The EN1 and EN2 pins can be used to select the proper
Power Sequencing Mode required by the powered system or
to disable the power sequencing (refer to Table 5 ).
Intrinsic Operation
For both the LDO and switcher, whenever the output
voltage is below the regulation point, the LDO external Pass
MOSFET is on, or the buck high side MOSFET is on at a duty
cycle controlled by the switcher. Because these devices are
MOSFETs, current can flow in either direction, balancing the
voltages via the common supply pin. The ability to maintain
the MOSFETs on is dependent on the available gate voltage,
and thus the size of the boost regulator storage capacitor.
34701
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
23
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