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| 型号： | MIC2131-4YTSE |
| 厂商： | Micrel Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16TSSOP |
| 标准包装： | 94 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 440kHz |
| 占空比： | 80% |
| 电源电压： | 8 V ~ 40 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 1091 (CN2011-ZH PDF) |
| 其它名称： | 576-3099-5 |
Micrel, Inc.
MIC2130/1
Control Loop Stability and
Compensation
G PwrS (s) =
? V SW
? d(s)
=
V Out
? d(s) * D
=
V Out
D Max * D
Gain of the
Figure 10 shows the simplified system schematic. The
Power Stage
1 +
+
internal transconductance error amplifier is used for
compensating the voltage feedback loop by placing a
capacitor (C1) in series with a resistor (R1) and another
capacitor C2 in parallel from the COMP pin-to-ground.
(Note: Ceramic output caps may require type III
compensation).
G Flt (s) =
where:
1 + sR esr C out
s s 2
2
Q ω 0 ω 0
Gain of the Filter
E stored
V REF
V FB
gm
V COMP
R1
C1
C2
PWM
Comparator
D (s)
V RAMP
R HS
V IN
V SW
L
C
R ESR
V OUT
R LOAD
Q =
and
ω 0 =
=
E Lost
1
LC out
R Load
L/C out
F esr =
(Parallel loaded)
1
2 π R esr C out
R LS
Figure 10 Simplified System Schematic
H(s) =
network
R LS
R LS + R HS
=
V ref
V out
Gain of the feedback
D Max V out V out
=
=
In order to have a stable system when the gain of T(s) =
1 ? (0db) the phase has to be greater (less negative)
than -180°. The amount the phase is greater than -180°
is called the phase margin, typically 30 to 60 and is a
key parameter predicting the stability of the system and
how much overshoot and undershoot the system
exhibits during transients.
The open loop transfer function is:
T(s) = G ea (s) x G PWMcomp (s) x G Pwrs (s) x G flt (s) x H fb (s)
And the phase is:
∠ T(s) = θ T (s) = θ ea + θ PWMcomp + θ PwrS + θ Flt + θ fb
For simplicity, combine the PWM comparator gain and
the Power stage gain and call it the modulator gain.
G Mod (s) = G PWMcomp (s) * G PWRsw (s)
therefore;
*
? V ramp D * D Max ? V ramp * D
T(s) = G ea (s) x G Mod (s) x G flt (s) x H fb (s) and
θ T (s) = θ ea + θ Mod + θ flt + θ fb
The phase of the open loop is the phase of all the blocks
in the loop added together.
V REF
V E
G ea (s) =
g m Z COMP
V COMP
G PWMComp
D (s)
G PWRS
V SW
G FLT
V OUT
The phase of T(s) is
θ T (s) = θ ea + θ PWMcomp + θ PwrS + θ Flt + θ fb
V FB
T(s)
H(s)
θ T (s) = θ ea + θ Mod + θ fb
Where θ ea = ? θ pole0 + θ Zero1 ? θ pole1
Figure 11 System Block Diagram
In the system block diagram in figure 11
θ pole0 = phase lag due to the pole at the origin
θ Zero1 =phase lead due to Zero1
? ?
? ?
? 1 ? ? 1 ?
= ? ? R1 +
sC 1 ? ?
G PWMcomp (s) =
=
=
G ea (s) = g m x Z comp Gain of the Error amp
where g m =1.5ms and
Z comp ?
? ? sC 2 ?
? D D Max 0.85
Gain of the PWM comparator
April 2008
? V comp ? V ramp 2.1 ? 1.1
= 0.85
16
θ pole1 = phase lag due to pole1
θ PWMcomp = 0 ° , θ PwrS = 0 ° θ fb = 0 ° therefore;
θ Mod = 0 °
The phase of the filter includes the complex poles of LC
and the Zero caused by the ESR of the C OUT .
The filter has 2 poles at F 0 and a zero at F esr
θ Flt = ? 180 ° at F 0 and +90° at F esr
M9999-042108-C
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