参数资料
型号: MIC2131-4YTSE
厂商: Micrel Inc
文件页数: 9/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16TSSOP
标准包装: 94
PWM 型: 电压模式
输出数: 1
频率 - 最大: 440kHz
占空比: 80%
电源电压: 8 V ~ 40 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
产品目录页面: 1091 (CN2011-ZH PDF)
其它名称: 576-3099-5
Micrel, Inc.
Theory of Operation
A voltage divider monitors the output voltage of the
converter then sensed at the inverting input of the error
amplifier. The non-inverting input of the error amplifier is
connected to the internal 0.7V reference and the two
inputs are compared to produce an analog error voltage.
This error voltage is then fed into the non-inverting input
of the PWM comparator and compared to the voltage
ramp (1.1V to 2.1V) to create the PWM pulses. The
PWM pulses propagate through to the MOSFET drivers
which drive the external MOSFETs to create the power
switching waveform at the set D (duty cycle). This is then
filtered by a power inductor and low ESR capacitor to
produce the output voltage where V OUT ≈ D*V IN . As an
example, due to a load increase or an input voltage
drop, the output voltage will instantaneously drop. This
will cause the error voltage to rise, resulting in wider
pulses at the output of the PWM comparator. The higher
Duty Cycle power switching waveform will cause an
associated rise in output voltage and will continue to rise
until the feedback voltage is equal to the reference and
the loop is again in equilibrium. As with any control
system, it is necessary to compensate this feedback
loop (by selecting the R and C values at the comp pin) in
order to keep the system stable. One of the tradeoffs for
stability is reduced transient regulation performance.
However, the MIC2130/31 has an additional feature to
correct this problem. The MIC2130/31 family features a
fast hysteretic control loop (FHyCL) which bypasses the
gm amp and the feedback compensation network during
fast line and load transients.
The fast hysteretic control loop (FHyCL) operates during
large transients to provide excellent line and load
regulation. Hysteretic mode is invoked when the output
voltage is detected to be ±6% of its regulated value. If
the input voltage step or output load step is large enough
to cause a 6% deviation in V OUT , then the additional
hysteretic control loop functions to return the output
voltage to its nominal set point in the fastest time
possible. This is limited only by the time constant of the
power inductor and output capacitor (an order of
magnitude faster than the gm loop). This scheme is not
used during normal operation because it creates
switching waveforms whose frequency is dependant on
V IN , passive component values and load current. Due to
its large noise spectrum it is only used during surges to
keep switching noise at a known, fixed frequency.
Soft Start
MIC2130/1
Figure 2. Hysteric Block Diagram
Figure 3. Hysteric Waveforms
Figure 4. Soft Start Circuit
April 2008
9
M9999-042108-C
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