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| 型号： | MIC2131-4YTSE |
| 厂商： | Micrel Inc |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16TSSOP |
| 标准包装： | 94 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 440kHz |
| 占空比： | 80% |
| 电源电压： | 8 V ~ 40 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 1091 (CN2011-ZH PDF) |
| 其它名称： | 576-3099-5 |
Micrel, Inc.
Example:
V IN = 24V; V OUT = 3.3V; I OUT = 10A; L = 7.3μH; C OUT =
660μF; Resr = 40m ? ; Fsw = 150KHz
The gain and phase of the modulator and filter is:
G Mod (s) x G flt (s)
MIC2130/1
The peak Gain equals the low freq gain plus the Q =
26.2 + 13.6 = 39.9db.
It is desired that T(s) (the open loop transfer function)
have a cross over frequency (Fco) of 1/10 the Switching
frequency at 15kHz. It is require that ∠ T(j 2 π Fco) (the
This is the gain
V OUT
V comp
(s) in Figure 12
phase of T(s) at Fco), to be greater than -180° by at
least the phase margin. By inspecting the Gain plot of
G Mod (s) at 15kHz, G Mod (s) has a gain of about 3.9db.
1 + R 1 ? s ? C 1
G ea ( s ) = g m ? ? ?
C 1 ? C 2 ? ?
G ea ( s ) = g m ? ?
? s ? ( C 1 ) ? ( 1 + R 1 ? C 2 ? s ) ?
A computer generated plot of G Mod (s) x G flt (s) is shown in
Figure 12.
Figure 12. Modulator Transfer Function
There is a -180° phase change near F 0. At frequencies
greater then F 0 the phase increases towards -90° due to
the zero of F esr . The phase effects of poles and zeros
start a decade below and finish a decade above the
frequency of a pole or zero. Therefore, at the frequency
of a pole or zero the phase effect is only half of the final
value. At the complex pole 2.3kHz the phase is -90 and
would be -180 at 23kHz if not for the +90 phase lead of
the zero at around 6kHz due to the esr of the filter
capacitors. (Actually, the phase gain plots reach their
final values asymptotically).
By inspecting Figure 12 the DC and low frequency gain
of G Mod = 20Log(0.85 x 24) = 26.2db; F 0 = 2.3kHz; F esr =
6kHz and Q is 13.6db.
Therefore, to make T(j2 π Fco) = 1 → 0db;
T(s) = G ea (s) x G Mod (s) x H fb (s) = 1 at Fco
H fb = Vref/Vout = 0.7/3.3 = 0.212 → -13.5db
|G ea | db = |T| db - |G Mod | db -|H fb | db = 0-3.9db – (-13.5db) =
9.6db ═ >3.02 The error amp needs 9db of gain at Fco.
Therefore g m x Z Comp = 3.02 at 15kHz.
The location of the error amp’s zero and poles are
selected in order to achieve the desired phase margin of
T(s). For the maximum phase boost at the cross over
Frequency (Fco), place the first Zero1 of the EA at
Fco/10 since the effect of its phase boost will be at the
maximum at Fco. Likewise, place the pole of the EA at
least 10 x Fco so the effects of its phase lag will be at a
minimum at Fco. Therefore, use R1 = 2k; C1 = 0.068μF;
C2 = 470pF.
g m Error Amplifier
Usually, it is undesirable to have high error amplifier gain
at high frequencies otherwise high frequency noise
spikes at large amplitude would be present at the output.
Hence, gain should be permitted to fall off at high
frequencies. At low frequency, it is desired to have high
open-loop gain to attenuate the power line ripple. Thus,
the error amplifier gain should be allowed to increase
rapidly at low frequencies.
The transfer function for the internal gm error amplifier
with R1, C1, and C2 at the comp pin is given by the
following equation:
? ?
? ?
? ? C 1 ? C 2 ? s ? ?
? s ? ( C 1 + C 2 ) ? ? 1 + R 1 ? ? ?
? ?
The above equation can be simplified by assuming
C2<C1,
? 1 + R 1 ? s ? C 1 ?
?
From the above transfer function, one can see that R1
and C1 introduce a zero and R1 and C2 a pole at the
following frequencies:
F zero1 = 1/2 π × R1 × C1 F pole1 = 1/2 π × C2 × R1
F pole@origin = 1/2 π × C1
April 2008
17
M9999-042108-C
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