参数资料
型号: MIC3003GML TR
厂商: Micrel Inc
文件页数: 13/75页
文件大小: 0K
描述: IC FOM MANAGEMENT W/CALIBR 24MLF
标准包装: 1,000
类型: 激光二极管控制器(光纤)
数据速率: 10Gbps
通道数: 1
电源电压: 3 V ~ 3.6 V
电流 - 电源: 2.3mA
工作温度: -40°C ~ 105°C
封装/外壳: 24-VFQFN 裸露焊盘,24-MLF?
供应商设备封装: 24-MLF?(4x4)
包装: 带卷 (TR)
安装类型: 表面贴装
Micrel, Inc.
Electrical Characteristics
MIC3003
Symbol
Parameter
Condition
Min
Typ
Max
Units
Control and Status I/O Timing, TXFAULT, TXDISABLE, RS0, RRSOUT, and RXLOS
tOFF
tON
tINIT
TXDISABLE Assert Time
TXDISABLE De-assert Time
Initialization Time
From input asserted to optical output
at 10% of nominal, C COMP = 10nF.
From input de-asserted to optical output
at 90% of nominal, C COMP = 10nF.
From power on or transmitter enabled to
optical output at 90% of nominal and
10
1
300
μs
ms
ms
TX_FAULT de-asserted. Note 10
tINIT2
tFAULT
tRESET
tLOSS_ON
tLOSS_OFF
tDATA
tPROP_IN
Power-on Initialization Time
TXFAULT Assert Time
Fault Reset Time
RXLOS Assert Time
RXLOS De-assert Time
Analog Parameter Data Ready
TXFAULT, TXDISABLE, RXLOS,
RS0, RS1 Input Propagation Time
From power on to APC loop-enabled.
From fault condition to TXFAULT
assertion. Note 10
Length of time TXDISABLE must be
asserted to reset fault condition.
From loss of signal to RXLOS asserted.
From signal acquisition to LOS
de-asserted.
From power on to valid analog
parameter data available. Note 10
Time from input change to
corresponding internal register bit set or
10
200
95
95
100
400
1
ms
μs
μs
μs
μs
ms
μs
cleared. Note 10
tPROP_OUT
TXFAULT, TRSOUT, TRRSOUT,
/INT, QGPO Output Propagation
From an internal register bit set or
cleared to corresponding output change.
1
μs
Time
Fault Comparators
Note 10
FLTTMR
Fault Suppression Timer Clock
Period
Note 10
0.475
0.5
0.525
ms
Accuracy
-3
+3
%/fs
tREJECT
VSAT
Glitch Rejection
Saturation Detection Threshold
Maximum length pulse that will not
cause output to change state. Note 10
High level
Low level
4.5
95
5
μs
%VDDA
%VDDA
Power-On Hour Meter
Timebase Accuracy
Resolution
0°C ≤ T A ≤ +70°, Note 10
–40°C ≤ T A ≤ +105°C
Note 10
+5
+10
10
-5
-10
%
%
hours
Non-Volatile (FLASH) Memory
t WR
Write Cycle Time, Note 11
Measured from the SMBus STOP
condition of a one-byte to eight-byte
13
ms
write transaction. Note 10
NVRAM Data Retention
100
years
Endurance
Maximum permitted number of write
10,000
cycles
cycles to any single NVRAM location
Notes:
10. Guaranteed by design and/or testing of related parameters. Not 100% tested in production.
11. The MIC3003 will not respond to serial bus transactions during an EEPROM write cycle. The host will receive a NACK response during t WR .
November 2009
13
M9999-111209-C
hbwhelp@micrel.com or (408) 955-1690
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