参数资料
| 型号： | MIC3003GML TR |
| 厂商： | Micrel Inc |
| 文件页数： | 21/75页 |
| 文件大小： | 0K |
| 描述： | IC FOM MANAGEMENT W/CALIBR 24MLF |
| 标准包装： | 1,000 |
| 类型： | 激光二极管控制器（光纤） |
| 数据速率： | 10Gbps |
| 通道数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 2.3mA |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘，24-MLF? |
| 供应商设备封装： | 24-MLF?（4x4） |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
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Micrel, Inc.
Alarms and Warnings as TXFAULT Source
Alarms and warnings are not sources for TXFAULT with
the default setting. To set alarms as a TXFAULT source
set OEMCFG4 bit 6 to 1. To set warnings as a
TXFAULT, source set OEMCFG4 bit 7 to 1. The alarms
and warnings TXFAULT sources can be masked
individually in the same way shown in Tables 7 and 8.
Latching of Alarms and Warnings
Alarms and warnings are latched by default, i.e., once
asserted the flags remain ON until the register is read or
TXDSABLE is toggled. If OEMCFG4 bit 5 is set to 1, the
warnings are not latched and will be set and reset with
the warning condition. Reading the register or toggling
TXDISABLE will clear the flag. If OEMCFG4 bit 4 is set
to 1, the alarms are not latched and will be set and reset
with the alarm condition. Reading the register or toggling
TXDISABLE will clear the flag.
SMBus Multipart Support
MIC3003
QGOP Pin Function
QGOP can be used in GOP mode as a general purpose
output by setting OEMCFG3 bit 7 to 0, or as in RESET
mode as a reset signal output by setting OEMCFG3 bit 7
to 1.
If RESET mode is selected, the reset signal state is
controlled by RSETOUT (A2:FFh bits [2-0]). By default,
these three bits are 000, and the QGPO output is
undriven (state: High). When the three bits are written to
111, QGPO’s open-drain output will be driven low for
125 μ s (typical), after which QGPO reenters the undriven
state. The RESETOUT field is cleared from 111 to 000
22.5 ms (typical) after the de-assertion edge of QGPO.
Other values of this delay may be selected by setting
TRSTCLR (OEMCFG2 bits [2-0]) to different values as
shown on table.
If Reset mode in OEMCFG3 is not selected, these three
bits have no function.
If more than one MIC3003 device shares the same serial
interface and multipart mode is selected on them
(OEMCFG5 bit 3 = 1), then pin 7 and pin 20 become
SMBus address bits 3 and 4 respectively. Therefore, the
parts should have a different setting on those pins to
create four address combinations based upon the state
of pin 7 and pin 20 state, (00, 01, 10, 11) where 0 is a
pull down to GND and 1 is a pull up to VCC. The parts
come from the factory with the same address (A0) and
multipart mode off (OEMCFG5 bit 3 is 0). After power
TRSTCLR
[2-0]
000
001
010
011
100
Delay from QGPO
Switching high to
RESETOUT clear
Zero delay
17.5 ms typical
22.5 ms typical (default)
27 ms typical
45 ms typical
up, write 1 to OEMCFG5 bit 3 to turn ON multipart mode,
which is done to all parts at the same time since they all
respond to serial address A0 at this point. With multipart
mode on, the parts have now different addresses based
on the states of pins 7 and 20. Another option is to
access each part individually, set their single mode
address in OEMCFG2 bits [4-7] to different values and
then turn off multipart mode to return to normal mode
where the parts have new different addresses.
Table 9. RESETOUT Clear Delay
November 2009
21
M9999-111209-C
hbwhelp@micrel.com or (408) 955-1690
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