参数资料
| 型号： | MIC5167YML TR |
| 厂商： | Micrel Inc |
| 文件页数： | 14/23页 |
| 文件大小： | 0K |
| 描述： | IC REG SYNC BUCK 6A 1MHZ 24-MLF |
| 标准包装： | 1 |
| 应用： | 转换器，DDR，QDR |
| 输入电压： | 2.6 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 最低可调至 0.6V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，24-MLF? |
| 供应商设备封装： | 24-MLF?（4x4） |
| 包装： | 标准包装 |
| 其它名称： | 576-3793-6 |
Micrel, Inc.
From that, the loss in efficiency due to inductor
resistance can be calculated as follows:
MIC5167
The circuit in Figure 5 describes the operation of the
current limit circuit. Since the actual R DS(ON) of the P-
Channel MOSFET varies part-to-part, over temperature
V OUT × I OUT
? ( V OUT × I OUT ) + L PD
Efficiency Loss = ? 1 ? ? ?
? ? × 100
? ? ?
? ?
? ?
? ?
?
and with input voltage, simple IR voltage detection is not
employed. Instead, a smaller copy of the Power
MOSFET (Reference FET) is fed with a constant current
which is a directly proportional to the factory set current
limit. This sets the current limit as a current ratio and
Efficiency loss due to DCR is minimal at light loads and
gains significance as the load is increased. Inductor
selection becomes a trade-off between efficiency and size
in this case.
Alternatively, under lighter loads, the ripple current due to
the inductance becomes a significant factor. When light
load efficiencies become more critical, a larger inductor
value maybe desired. Larger inductances reduce the peak-
to-peak inductor ripple current, which minimize losses.
Compensation
The MIC5167 has a combination of internal and external
thus, is not dependant upon the R DS(ON) value. ? Current
limit is set to nominal value. Variations in the scale factor
K between the Power PFET and the reference PFET
used to generate the limit threshold account for a
relatively small inaccuracy.
PVIN
HSD
stability compensation to simplify the circuit for small,
high efficiency designs. In such designs, voltage mode
conversion is often the optimum solution. Voltage mode
is achieved by creating an internal 1MHz ramp signal
and using the output of the error amplifier to modulate
the pulse width of the switch node, thereby maintaining
output voltage regulation. With a typical gain bandwidth
CONTROL
LOGIC
CLOCK
I LIMIT/K
PVIN
LSD
SW
PGND
of 100-200kHz, the MIC5167 is capable of extremely fast
transient responses.
The MIC5167 is designed to be stable with a typical
application using a 1μH inductor and a 100μF ceramic
(X5R) output capacitor. These values can be varied
dependant upon the tradeoff between size, cost and
efficiency, keeping the LC natural frequency
1
( ) ideally less than 26kHz to ensure
2 × π × L C
stability can be achieved. The minimum recommended
inductor value is 0.4μH and minimum recommended
output capacitor value is 100μF. The tradeoff between
changing these values is that with a larger inductor,
there is a reduced peak-to-peak current which yields a
greater efficiency at lighter loads. A larger output
capacitor will improve transient response by providing a
larger hold up reservoir of energy to the output.
Current Limit
The MIC5167 is protected against overload in two
stages. The first is to limit the current in the P-channel
switch; the second is over temperature shutdown.
Current is limited by measuring the current through the
high-side MOSFET during its power stroke and
immediately switching off the driver when the preset limit
is exceeded.
Figure 5. Current-Limit Detail
Thermal Considerations
The MIC5167 is packaged in a MLF ? 4mm x 4mm, a
package that has excellent thermal performance. This
maximizes heat transfer from the junction to the exposed
pad (ePAD) which connects to the ground plane. The
size of the ground plane attached to the exposed pad
determines the overall thermal resistance from the
junction to the ambient air surrounding the printed circuit
board.
Sequencing and Tracking
The MIC5167 provides PG and EN/DLY pins to provide
sequencing and turn on delay capability for connecting
multiple voltage regulators together.
Enable/DLY Pin
The Enable pin contains a trimmed, 1μA current source
which can be used with a capacitor to implement a fixed
desired delay in some sequenced power systems. The
threshold level for power on is 1.24V with a hysteresis of
20mV.
January 2012
14
M9999-012312-B
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