参数资料
| 型号： | MIC5167YML TR |
| 厂商： | Micrel Inc |
| 文件页数： | 2/23页 |
| 文件大小： | 0K |
| 描述： | IC REG SYNC BUCK 6A 1MHZ 24-MLF |
| 标准包装： | 1 |
| 应用： | 转换器，DDR，QDR |
| 输入电压： | 2.6 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 最低可调至 0.6V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，24-MLF? |
| 供应商设备封装： | 24-MLF?（4x4） |
| 包装： | 标准包装 |
| 其它名称： | 576-3793-6 |
Micrel, Inc.
Ordering Information
MIC5167
Part Number
Voltage
Junction Temperature Range
Package
Lead Finish
MIC5167YML
Adjustable
–40°C to +125°C
24-Pin 4x4 MLF
?
Pb-Free
MLF is a GREEN RoHS-compliant package. Lead finish is NiPdAu. Mold compound is Halogen Free.
Note:
?
Pin Configuration
24-Pin 4mm x 4mm MLF ? (ML)
Pin Description
Pin Number
1, 6, 13, 18
2
3
4
5
14
15
16
Pin Name
PVIN
EN/DLY
VDDQ
VREF
PG
FB
COMP
SGND
Description
Power Supply Voltage (Input): The PVIN pins are the input supply to the internal P-Channel
Power MOSFET. A 22μF ceramic is recommended for bypassing at each PVIN pin. The SVIN
pin must be connected to the PVIN pin.
Enable/Delay (Input): This pin is internally fed with a 1μA current source from SVIN. A delayed
turn on is implemented by adding a capacitor to this pin. The delay is proportional to the capacitor
value. The internal circuits are held off until EN/DLY reaches the enable threshold of 1.24V. This
pin is pulled low when the input voltage is lower than the UVLO threshold.
VDDQ (Input): VDDQ is connected to an internal precession divider which provides the reference
voltage (VREF).
VTT Reference (Output): This output provides an output of the internal reference voltage
VDDQ/2. Connect a 100pF capacitor to ground at this pin.
PG (Output): This is an open drain output that indicates when the output voltage is within ±15%
of its nominal voltage. The PG flag is asserted without delay when the enable is set low or when
the output goes outside ±15% the window threshold.
Feedback (Input): Input to the error amplifier.
Compensation pin (Input): The MIC5167 uses an internal compensation network containing a
fixed-frequency zero (phase lead response) and pole (phase lag response) which allows the
external compensation network to be much simplified for stability. The addition of a single
capacitor and resistor to the COMP pin will add the necessary pole and zero for voltage mode
loop stability using low value, low-ESR ceramic capacitors.
Signal Ground: Internal signal ground for all low power circuits.
January 2012
2
M9999-012312-B
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