参数资料
型号: MICRF507YML TR
厂商: Micrel Inc
文件页数: 19/47页
文件大小: 0K
描述: TXRX FSK LOW PWR W/AMP 32MLF
特色产品: MICRF507 Low-Power FSK Transceiver
标准包装: 1
系列: RadioWire®
频率: 470MHz ~ 510MHz
数据传输率 - 最大: 200kbps
调制或协议: FSK
应用: AMR,ISM,SRD
功率 - 输出: 10dBm
灵敏度: -113dBm
电源电压: 2 V ~ 2.5 V
电流 - 接收: 12mA
电流 - 传输: 21.5mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘,32-MLF?
包装: 标准包装
其它名称: 576-3694-6
MICRF507YML TRDKR
MICRF507YML TRDKR-ND
Micrel, Inc.
MICRF507
Mode
Sync_en
DATACLK
DATAIXO
Direction
Signal
Direction
Signal/Function
Transmit
0
1
Output
Output
0
BitRate clock
Input
Input
Modulates carrier directly
(asynchronously)
Sampled at rising edge of BitRate
clock; latched output modulates
carrier
0
Output
0
Output
Raw output from demodulator
Receive
1
Output
Clock recovered by bit
synchronizer
Output
Filtered and latched demodulator
output; transitions occur at rising
edge of DATACLK
Table 8. Synchronizer Mode and Data Interface
In sync mode (Sync_en bit set to 1), the transmitted bit
stream is clocked with the precision of the MICRF507’s
crystal oscillator, which relaxes timing accuracy
requirements on the data source. During reception, the
synchronizer ensures that transitions of DATAIXO occur
only at rising edges of DATACLK, without edge jitter or
internal glitches. Receiver sensitivity values given in the
Electrical Characteristics table are measured with Sync_en
= 1; with Sync_en = 0, as much as 3-6 dB of sensitivity
could be lost.
Sync_en = 0
When Sync_en = 0, the input signal at DATAIXO
modulates the transmitter directly during transmission and
the output signal from DATAIXO is the raw demodulator
output. DATACLK remains fixed at a logic low level during
both transmission and reception.
Sync_en = 1
During transmission when Sync_en = 1 the data bit stream
entering DATAIXO is buffered with a flip-flop strobed at the
rising edge of BITRATE_CLK, and the output of the flip-
flop modulates the transmitter. BITRATE_CLK is brought
out at the DATACLK output. Figure 10 shows the
relationship of DATACLK and DATAIXO transitions.
Figure 10. Data Interface in Transmit Mode
During reception, the bit synchronizer recovers the
received signal’s clock. This recovered clock strobes a flip-
flop that samples in mid-bit-period the demodulated and
filtered bit stream. The DATACLK output brings out the
recovered clock. DATAIXO (an output during reception)
brings out the synchronized data stream, which has its
transitions at rising edges of DATACLK. See Figure 11.
Figure 11. Data Interface in Receive Mode
By being in control of bit timing, the MICRF507 is
effectively the “master.” For maximum timing margin, the
microcontroller, as the “slave,” can present or sample
(during transmit and receive, respectively) each new bit at
the DATAIXO pin at falling edges of DATACLK.
Additional Considerations in the Use of Synchronizer
(Sync_en = 1)
Two clock signals, BITRATE_CLK and BITSYNC_CLK,
must be properly programmed when using the
synchronizer. BITRATE_CLK, used in transmission, must
be set to a frequency equal to the bit rate.
BITSYNC_CLK, used in reception, must have a frequency
16 times the bit rate. These frequencies are controlled by
the crystal oscillator frequency and the settings of register
fields, as described in the “Clock Generation” section. Bit
clocking of the incoming signal must agree with the
receiver’s local clocking within ± 2.5% (easily met with 100
PPM or better crystals). For example, if f BITSYNC_CLK is
16x19.231kbps, the incoming bit rate can be between
0.975x19.231kbps to 1.025x19.231kbps.
All incoming messages must start with a 0101… preamble
so that the synchronizer can acquire the incoming clock. A
24-bit preamble is typically used; a minimum of 22 bits is
required.
October 2, 2013
19
Revision 2.2
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