参数资料
型号: MICRF507YML TR
厂商: Micrel Inc
文件页数: 23/47页
文件大小: 0K
描述: TXRX FSK LOW PWR W/AMP 32MLF
特色产品: MICRF507 Low-Power FSK Transceiver
标准包装: 1
系列: RadioWire®
频率: 470MHz ~ 510MHz
数据传输率 - 最大: 200kbps
调制或协议: FSK
应用: AMR,ISM,SRD
功率 - 输出: 10dBm
灵敏度: -113dBm
电源电压: 2 V ~ 2.5 V
电流 - 接收: 12mA
电流 - 传输: 21.5mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘,32-MLF?
包装: 标准包装
其它名称: 576-3694-6
MICRF507YML TRDKR
MICRF507YML TRDKR-ND
Micrel, Inc.
Figure 14. Second and Third Order Loop Filter
Table 12 shows three different loop filter designs, the first
two for VCO modulation and the last one for modulation
using the internal dividers. The component values are
calculated with RF frequency = 490MHz, VCO gain =
67MHz/V as seen by the PLL, and desired phase margin =
56o. Other settings are shown in the table. The VARIN pin
capacitance (pin 29) of 6pF can be neglected for the two
filters with lowest bandwidth (which have R2=0 and
relatively large values of C1). For other loop bandwidth
and phase detector values, use the loop filter calculation
tool in RF Testbench software available on Micrel’s
website.
MICRF507
Lock Detect
A lock detector can be enabled by setting LD_en = 1.
When pin LD is high, it indicates that the PLL is in lock.
After a control word is loaded LD will (typically) go low,
then high again when the synthesizer has locked. LD also
goes low initially when the PA (power amplifier) is turning
on.
After the transceiver has been put into Receive or
Transmit mode, or after the power amplifier has been
turned on, a low-to-high transition at LD can serve as an
indicator that the synthesizer frequency has stabilized.
Encoded
PLL
Charge
Phase
Bit Rate
(kbps)
BW
(kHz)
Pump
( μ A)
Detector
Freq. (kHz)
C1
C2
R1
R2
C3
VCO
VCO
Divider
>8
>32
<6.5
0.8
3.2
13
125
125
500
100
100
500
10nF
680pF
390pF
100nF
6.8nF
8.2nF
6.2k?
22k?
5k?
0
0
68k?
NC
NC
18pF
Table 12. Loop Filter Component Values
October 2, 2013
23
Revision 2.2
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