参数资料
型号: MICRF507YML TR
厂商: Micrel Inc
文件页数: 30/47页
文件大小: 0K
描述: TXRX FSK LOW PWR W/AMP 32MLF
特色产品: MICRF507 Low-Power FSK Transceiver
标准包装: 1
系列: RadioWire®
频率: 470MHz ~ 510MHz
数据传输率 - 最大: 200kbps
调制或协议: FSK
应用: AMR,ISM,SRD
功率 - 输出: 10dBm
灵敏度: -113dBm
电源电压: 2 V ~ 2.5 V
电流 - 接收: 12mA
电流 - 传输: 21.5mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘,32-MLF?
包装: 标准包装
其它名称: 576-3694-6
MICRF507YML TRDKR
MICRF507YML TRDKR-ND
Micrel, Inc.
Divider Modulation
When Modulation[1:0] = 10, two sets of divider values
need to be programmed. The divider values stored in the
M0, N0, and A0 registers are selected to transmit a ‘0’ and
the M1, N1, and A1 registers are selected to transmit a ‘1’.
MICRF507
as to “round” the waveform and reduce the transmission
spectral width.
The amplitude of the modulating waveform, and therefore
frequency deviation, is determined by the modulation clock
frequency (controlled by the crystal oscillator frequency
and the register fields Refclk_K, and Mod_ClkS), the
f RF0 = f XCO
f RF1 = f XCO
16 × N0 + A0
2M0
16 × N1 + A1
2M1
charge/discharge current (controlled by the register field
Mod_I), and the setting of an attenuator (controlled by the
register field Mod_A). The effects of these factors are
explained and quantified belo. A filter is provided to
optimize transmit bandwidth, the proper setting of which is
also explained below.
The synthesizer is a negative feedback loop that
suppresses perturbations inside the loop (including the
f RF0 + f RF1
f RF =
The carrier frequency that a receiver must be set to in
order to receive the above transmitted signal is:
2
and the single-sided deviation is:
modulating varactor control voltage) below its bandwidth.
The PLL will not allow modulation unless its transient
response is slower than the bitstream pulses. Frequency
deviation is a high-pass response to modulation. This
means that when VCO modulation is used, the loop
bandwidth must be less than the lowest baseband spectral
component of the bitstream. It also means that the
f DEV =
f RF1 ? f RF0
2
bitstream must be DC-free (have an equal number of ones
and zeros). See “DC Balanced Line Coding” section.
The PLL must lock to a new frequency upon every
transition in the transmitted bitstream and therefore, needs
a high bandwidth, at least twice the bit rate.
VCO Modulation and the Modulator
VCO Modulation is selected when Modulation[1:0] = 00.
The modulator generates a waveform with programmable
amplitude and shape. This waveform is fed into a
modulation varactor in the VCO, which performs the
desired frequency modulation. The synthesizer operates
with A=A0, M=M0, and N=N0.
To create the modulating waveform the modulator charges
and discharges a capacitor, controlled by a modulator
clock. As shown in Figure 19, each transition of the
waveform takes four periods of the modulator clock.
Charge/discharge current, and therefore slope, varies so
Figure 19. Modulator Waveform and Clock
October 2, 2013
30
Revision 2.2
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