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参数资料
| 型号： | MK1492-04RTRLF |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 75 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, SSOP-28 |
| 文件页数： | 5/8页 |
| 文件大小： | 102K |
| 代理商： | MK1492-04RTRLF |
MK1492-04
OPTi Firestar+ Clock Source
MDS1492-04C
5
Revision 4308
Printed 4/30/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY INFORMATION
ICRO
CLOCK
Power-On Default Conditions
Input Pin#
Function
Default Condition
5
OE
M
All outputs enabled.
15
CPUS#
1
HOST clocks running.
16
PCISTP#
1
PCI clocks running.
19
DS
1
HOST7, HOST8 disabled.
21
SEL0
1
48/14.3 (pin 21) set to 48 MHz
22
LE
1
Low EMI function OFF
24
FS
1
HOST frequency = 66.66 MHz.
25
SEL1
M
F1 (pin 28) set to 14.318 MHz
27
CSSS
1
Allows CPU STOP mode. Refer to Power Down Control Table on page 2.
28
PEN
M
PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock (33.33 MHz).
General I 2C Serial Interface Operation
A. The I2C address for the MK1492-04 is D2(hex). For the clock generator to be addressed by an I2C
controller, this address must be sent as a start sequence, with an acknowledge bit between each byte as
shown below.
MK1492-04 Address (7 bits)
+ R/W# bit
8 bits dummy
ACK
Command code
ACK
Byte count
ACK
D2(hex)
Then Bytes 0, 1, 2, 3, 4, 5
in sequence unless a STOP
condition is encountered.
B. The MK1492-04 is an I2C slave component only. It does not have any read-back capability.
C. The data transfer rate supported by the MK1492-04 is 100K bits/sec (standard mode).
D. The input is operating at 3.3 V logic levels (refer to Electrical Specifications Table).
E. The data byte format is 8-bit bytes.
F. To simplify the I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent,
but the data is ignored for those two bytes. The data is loaded until a Stop condition is encountered.
G. In the Power Down mode (CPUS# Low, or “0”), the SDATA and SCLK pins are tristated and the
internal data latches maintain all prior programming information. Coming out of the Power Down
mode does not change the I2C registers; they are reset only when VDD is cycled.
H. At power-on, all registers are set to a default condition. See Byte 0 detail for its default condition;
Bytes 1 through 5 default to a 1 (Enabled output state).
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