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参数资料
| 型号： | MPC5601PEF0VLL4 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-100 |
| 文件页数： | 89/95页 |
| 文件大小： | 1694K |
| 代理商： | MPC5601PEF0VLL4 |
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MPC5602P Microcontroller Data Sheet, Rev. 4.1
Freescale Semiconductor
9
The flash memory module provides the following features:
As much as 320 KB flash memory
— 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory
— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory
— Full Read-While-Write (RWW) capability between code flash memory and data flash memory
Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to
prefetch code or data or both)
Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page buffer miss at 64 MHz
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
Hardware and software configurable read and write access protections on a per-master basis
Configurable access timing allowing use in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for
emulation of other memory types
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page sizes
— Code flash memory: 128 bits (4 words)
— Data flash memory: 32 bits (1 word)
ECC with single-bit correction, double-bit detection for data integrity
— Code flash memory: 64-bit ECC
— Data flash memory: 32-bit ECC
Embedded hardware program and erase algorithm
Erase suspend and program abort
Censorship protection scheme to prevent flash memory content visibility
Hardware support for EEPROM emulation
1.5.5
Static random access memory (SRAM)
The MPC5602P SRAM module provides up to 20 KB of general-purpose memory.
ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family devices containing
an e200z6 core and 64-bit wide ECC.
The SRAM module provides the following features:
Supports read/write accesses mapped to the SRAM from any master
Up to 20 KB general purpose SRAM
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if
back-to-back with a read to same memory block
1.5.6
Interrupt controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems. The INTC handles 128 selectable-priority interrupt sources.
For high-priority interrupt requests, the time from the assertion of the interrupt request by the peripheral to the execution of the
interrupt service routine (ISR) by the processor has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR has to be executed. It also provides a wide number of priorities so that
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相关代理商/技术参数 |
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| MPC5601PEF0VLL4R | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC5602P Microcontroller Data Sheet |
| MPC5601PEF0VLL6R | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC5602P Microcontroller Data Sheet |
| MPC5602B | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Qorivva MPC560xB/C/D Family |
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