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参数资料
| 型号： | MPC7400RX350TX |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 34/44页 |
| 文件大小： | 744K |
| 代理商： | MPC7400RX350TX |
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MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
1.2 Features
This section summarizes features of the MPC7400’s implementation of the PowerPC architecture. Major
features of the MPC7400 are as follows:
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving 2 speculations)
— Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch
delay slots
Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)
— Dispatch two instructions to eight independent units (system, branch, load/store, xed-point
unit 1, xed-point unit 2, oating-point, AltiVec permute, AltiVec ALU)
— Serialization control (predispatch, postdispatch, execution serialization)
Decode
— Register le access
— Forwarding control
— Partial instruction decode
Completion
— 8 entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization and all instruction ow changes
Fixed-point units (FXUs) that share 32 GPRs for integer operands
— Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
Three-stage oating-point unit and a 32-entry FPR le
— Support for IEEE-754 standard single and double-precision oating-point arithmetic
— 3 cycle latency, 1 cycle throughput (single or double precision)
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
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