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参数资料
| 型号： | MPC7400RX350TX |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 5/44页 |
| 文件大小： | 744K |
| 代理商： | MPC7400RX350TX |
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MPC7400 RISC Microprocessor Hardware Specications
13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.4.2.1 Clock AC Specications
Table 8. Clock AC Timing Specifications
At recommended operating conditions (See Table 3)
Characteristic
Symbol
Maximum Processor Core
Frequency
Unit
Notes
350 MHz
400 MHz
Min
Max
Min
Max
Processor frequency
fcore
300
350
300
400
MHz
1
VCO frequency
fVCO
600
700
600
800
MHz
1
SYSCLK frequency
fSYSCLK
25
100
25
100
MHz
1
SYSCLK cycle time
tSYSCLK
10
40
7.5
40
ns
SYSCLK rise and fall time
tKR & tKF
—
1.0
—
1.0
ns
2
tKR & tKF
—
0.5
—
0.5
ns
3
SYSCLK duty cycle
measured at OVdd/2
tKHKL/tSYSCLK
40
60
40
60
%
4
SYSCLK jitter
—
±150
—
±150
ps
5
Internal PLL relock time
—
100
—
100
s6
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the
resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not
exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–
3] signal description in Section 1.8.1, “PLL Conguration,” for valid PLL_CFG[0–3] settings
2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OVdd = 3.3V
nominal.
3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V when OVdd = 1.8V
nominal.
4. Timing is guaranteed by design and characterization.
5. This represents total input jitter—short term and long term combined—and is guaranteed by
design.
6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum
amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the
power-on reset sequence. This specication also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
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