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参数资料
| 型号： | MPC7400RX350TX |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, CBGA360 |
| 封装： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件页数： | 8/44页 |
| 文件大小： | 744K |
| 代理商： | MPC7400RX350TX |
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16
MPC7400 RISC Microprocessor Hardware Specications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Notes:
1. All input specications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the
input SYSCLK. All output specications are measured from the midpoint of the rising edge of SYSCLK to the
midpoint of the signal in question. All output timings assume a purely resistive 50 ohm load (See Figure 4). Input and
output timings are measured at the pin;time-of-ight delays must be added for trace lengths, vias, and connectors in the
system.
2. The symbology used for timing specications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V)
relative to the SYSCLK reference (K) going to the high(H) state or input setup time. And tKHOV symbolizes the time
from SYSCLK(K) going high(H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the
time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of the
reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output
went invalid (OX). For additional explanation of AC timing specications in Motorola PowerPC microprocessors, see
the application note “Understanding AC Timing Specications for PowerPC Microprocessors.”
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5).
4. This specication is for conguration mode select only. Also note that the HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0-3]
7. Address/Transfer Attribute signals are composed of the following—A[0–31], AP[0–3], TT[0–4], TBST, TSIZ[0–2],
GBL, WT, CI
8. Data signals are composed of the following—DH[0–31], DL[0–31]; Data Parity signals are composed of DP[0–7].
9. All other input signals are composed of the following— AACK, BG, CKSTP_IN, DBG, DBWO/DTI[0], DTI[1-2],
HRESET, INT, MCP, QACK, SMI, SRESET, TA, TBEN, TEA, TLBISYNC.
10. All other output signals are composed of the following— BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV
11. According to the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are
asserted low then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for
TS, ABB or DBB is 0.5* tSYSCLK, i.e. less than the minimum tSYSCLK period, to ensure that another master asserting
TS, ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold timing is
tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed by design.
12. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period
immediately following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low.
Any master asserting it low in the rst clock following AACK will then go to high-Z for one clock before precharging
it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tsysclk; i.e.
it should be high-Z as shown in Figure 6 before the rst opportunity for another master to assert ARTRY. Output valid
and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is
guaranteed by design.
13. Guaranteed by design and not tested.
Table 9. Processor Bus AC Timing Specifications1 (Continued)
At Vdd=AVdd=1.8V±100mV; 0
≤ Tj ≤ 105°C, OVdd = 3.3V±165mV or OVdd = 2.5V±100mV or OVdd=1.8V±100mV
Parameter
Symbol2
350, 400 MHz
Unit
Notes
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For More Information On This Product,
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