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参数资料
| 型号： | MPC7450RX600LX |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 600 MHz, RISC PROCESSOR, CBGA483 |
| 封装： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件页数： | 42/60页 |
| 文件大小： | 1296K |
| 代理商： | MPC7450RX600LX |
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MPC7450 RISC Microprocessor Hardware Specifications
47
System Design Information
The MPC7450 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock
frequency of the MPC7450. The core-to-L3 frequency divisor for the L3 PLL is selected through the
L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency
supported by the external RAMs, the frequency of the MPC7450 core, and timing analysis of the circuit
board routing. Table 19 shows various example L3 clock frequencies that can be obtained for a given set of
core frequencies.
0
1100
8x
2x
266
(533)
400
(800)
533
(1066)
600
(1200)
664
(1328)
1
0111
9x
2x
300
(600)
450
(900)
600
(1200)
675
(1350)
747
(1494)
1
1010
10x
2x
333
(666)
500
(1000)
667
(1333)
750
(1500)
1
1001
11x
2x
366
(733)
550
(1100)
733
(1466)
1
1011
12x
2x
400
(800
600
(1200)
1
0101
13x
2x
433
(866)
650
(1300)
1
1100
14x
2x
466
(933)
700
(1400)
1
0001
15x
2x
500
(1000)
750
(1500)
1
1101
16x
2x
533
(1066)
0
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly
0
1111
PLL off
PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7450; see Section 1.5.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must
be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold
time tIXKH (see Table 10). The result will be that the processor bus frequency will be one-half SYSCLK while the
internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use
only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7450 regardless of the SYSCLK input.
Table 18. MPC7450 Microprocessor PLL Configuration Example (Continued)
PLL_EXT
PLL_CFG
[0:3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3 MHz
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
83 MHz
Bus
100 MHz
Bus
133 MHz
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