- 您现在的位置：买卖IC网 > PDF目录67998 > MPC7450RX600LX (MOTOROLA INC) 32-BIT, 600 MHz, RISC PROCESSOR, CBGA483 PDF资料下载
参数资料
| 型号： | MPC7450RX600LX |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 600 MHz, RISC PROCESSOR, CBGA483 |
| 封装： | 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件页数： | 47/60页 |
| 文件大小： | 1296K |
| 代理商： | MPC7450RX600LX |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页当前第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
MPC7450 RISC Microprocessor Hardware Specifications
51
System Design Information
MPC7450, 483 BGA, the pins that must be pulled up to OVDD are: LSSD_MODE and TEST[0:5]; the pins
that must be pulled down are: L1_TSTCLK and TEST[6].
In addition, the MPC7450 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7 k
–1 k) if it is used by the system. This pin is CKSTP_OUT.
If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250
(see
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Since the MPC7450
must continually monitor these signals for snooping, this float condition may cause excessive power draw
by the input receivers on the MPC7450 or by other receivers in the system. It is recommended that these
signals be pulled up through weak (4.7 k
) pull-up resistors by the system, or that they may be otherwise
driven by the system during inactive periods of the bus. The snooped address and transfer attribute inputs
are: A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL.
If extended addressing is not used, A[0:3] are unused and must be be pulled low to GND through weak
pull-down resistors. If the MPC7450 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak
pull-down resistors.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: D[0:63] and DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
The L3 interface does not normally require pull-up resistors.
1.9.8 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC7450
are available on the internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all PowerPC implementations. While it is possible to force
the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface
is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply
tying TRST to HRESET is not practical.
The COP function of PowerPC processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these signals
with logic.
The arrangement shown in Figure 25 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. The pull-down resistor on TRST ensures that the JTAG
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8241TZQ200D | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LVR266D | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LVR166D | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241LZQ166D | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357 |
| MPC8241TZQ166D | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA357 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC7455 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC7457 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC7457EC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC745BPX300LE | 功能描述:微处理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC745BPX350LE | 功能描述:微处理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。