MPC7450 RISC Microprocessor Hardware Specifications
49
System Design Information
part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and
excessive current can flow through these diodes. If the system power supply design does not control the
voltage sequencing, the circuit shown in
Figure 23 can be added to meet these requirements. The 30BF10
diodes (see
Figure 23) control the maximum potential difference between the external bus and core power
supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on power-down.
Figure 23. Example Voltage Sequencing Circuit
1.9.4 Decoupling Recommendations
Due to the MPC7450 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7450 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC7450 system, and the MPC7450 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, and GVDD pin of the MPC7450. It is also recommended that these decoupling capacitors
receive their power from separate VDD, OVDD/GVDD, and GND power planes in the PCB, utilizing short
traces to minimize inductance.
These capacitors should have a value of 0.01 F or 0.1 F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where
connections are made along the length of the part. Consistent with the recommendations of Dr. Howard
Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to
previous recommendations for decoupling PowerPC microprocessors, multiple small capacitors of equal
value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, GVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These
bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response
time necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
1.9.5 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, OVDD, GVDD, and GND pins in the
MPC7450.
2.5 V
1.6 V
30BF10
1N5820
30BF10