参数资料
型号: MPC8245LZU266B
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件页数: 39/64页
文件大小: 940K
代理商: MPC8245LZU266B
44
MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
System Design Information
1.7
System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8245.
1.7.1
PLL Power Supply Filtering
The AVDD and AVDD2 power signals are provided on the MPC8245 to provide power to the peripheral
logic/memory bus PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the
power supplied to the AVDD and AVDD2 input signals should be filtered of any noise in the 500 kHz to
10 MHz resonant frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 27
using surface mount capacitors with minimum effective series inductance (ESL) is recommended for AVDD
and AVDD2 power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed
Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value
are recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important.
Figure 27. PLL Power Supply Filter Circuit
1.7.2
Decoupling Recommendations
Due to its dynamic power management feature, the large address and data buses, and its high operating
frequencies, the MPC8245 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC8245 system, and the MPC8245 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each
VDD, OVDD, GVDD, and LVDD pin of the MPC8245. It is also recommended that these decoupling
capacitors receive their power from dedicated power planes in the PCB, utilizing short traces to minimize
inductance. These capacitors should have a value of 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that
connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
VDD
AVDD or AVDD2
2.2 F
GND
Low ESL Surface Mount Capacitors
10
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