- 您现在的位置：买卖IC网 > PDF目录69036 > MPC8245LZU266B (MOTOROLA INC) 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352 PDF资料下载
参数资料
| 型号： | MPC8245LZU266B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件页数： | 42/64页 |
| 文件大小： | 940K |
| 代理商： | MPC8245LZU266B |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页当前第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
47
System Design Information
The programmable PCI output valid and output hold feature controlled by bits in the power management
configuration register 2 (PMCR2) <0x72> has changed slightly in the MPC8245. For the MPC8240, 3 bits,
PMCR2[6:4] = PCI_HOLD_DEL, are used to select 1 of 8 possible PCI output timing configurations.
PMCR2[6:5] are software controllable but initially are set by the reset configuration state of the MCP and
CKE signals, respectively; PMCR2[4] can be changed by software. The default configuration for
PMCR2[6:4] = 0b110 since the MCP and CKE signals have internal pull-up resistors, but this default
configuration does not select 33 or 66 MHz PCI operation output timing parameters for the MPC8240; this
choice is made by software. For the MPC8245, only 2 bits in the power management configuration register 2
(PMCR2), PMCR2[5:4] = PCI_HOLD_DEL, control the variable PCI output timing. PMCR2[5:4] are
software controllable but initially are set by the inverted reset configuration state of the MCP and CKE
signals, respectively. The default configuration for PMCR2[5:4] = 0b00 since the MCP and CKE signals
have internal pull-up resistors and the values from these signals are inverted; this default configuration
selects 66 MHz PCI operation output timing parameters. There are four programmable PCI output timing
configurations on the MPC8245, see Table 11 for details.
Voltage sequencing requirements for the MPC8245 are similar to those for the MPC8240; however, there
are two changes which are applicable for the MPC8245. First, there is an additional requirement for the
MPC8245 that the non-PCI input voltages (Vin) must not be greater than GVDD or OVDD by more than
0.6 V at all times including during power-on reset (see caution 5 in Table 2). Second, for the MPC8245,
LVDD must not exceed OVDD by more than 3.0 V at any time including during power-on reset (see caution
There is no LAVDD input voltage supply signal on the MPC8245 since the SDRAM clock delay-locked loop
(DLL) has power supplied internally. Signal D17 should be treated as a no connect for the MPC8245.
1.7.7
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, then the COP reset signals must be merged into these signals
with logic.
The arrangement shown in Figure 28 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted
ensuring that the JTAG scan chain is initialized during power-on.
The COP header shown in Figure 28 adds many benefits—breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8260ACZUMIBB | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480 |
| MPC8260AZUPIBB | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480 |
| MPC8260AZUPJDB | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480 |
| MPC8260AZUMHBB | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480 |
| MPC8379EVRALGA | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8245LZU266D | 功能描述:微处理器 - MPU 266MHz 505.4MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245LZU300D | 功能描述:微处理器 - MPU 300MHz 570MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245LZU333D | 功能描述:微处理器 - MPU 333MHz 632.7MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245LZU350D | 功能描述:微处理器 - MPU 350MHz 665MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8245RZU400D | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Part Number Specification for the MPC8245ARZUnnnX Series |
发布紧急采购，3分钟左右您将得到回复。