参数资料
型号: MPC8245LZU266B
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件页数: 41/64页
文件大小: 940K
代理商: MPC8245LZU266B
46
MPC8245 Integrated Processor Hardware Specifications
MOTOROLA
System Design Information
Reset configuration pins should be tied to GND via 1-k
pull-down resistors to ensure a logic zero level is
read into the configuration bits during reset if the default logic-one level is not desired.
Any other unused active low input pins should be tied to a logic-one level via weak pull-up resistors
(2–10 k
) to the appropriate power supply listed in Table 17. Unused active high input pins should be tied
to GND via weak pull-down resistors (2–10 k
).
1.7.5
PCI Reference Voltage—LVDD
The MPC8245 PCI reference voltage (LVDD) pins should be connected to 3.3 ± 0.3 V power supply if
interfacing the MPC8245 into a 3.3-V PCI bus system. Similarly, the LVDD pins should be connected to
5.0 V ± 5% power supply if interfacing the MPC8245 into a 5-V PCI bus system. For either reference
voltage, the MPC8245 always performs 3.3-V signaling as described in the PCI Local Bus Specification
(Rev. 2.2). The MPC8245 tolerates 5-V signals when interfaced into a 5-V PCI bus system.
1.7.6
MPC8245 Compatibility with MPC8240
The MPC8245 AC timing specifications are backwards-compatible with those of the MPC8240, except for
the requirements of item 11 in Table 10. Timing adjustments are needed as specified for Tos
(SDRAM_SYNC_IN to sys_logic_clk offset) time requirements.
The MPC8245 does not support the SDRAM flow-through memory interface.
The nominal core VDD power supply changes from 2.5 V on the MPC8240 to 1.8/2.0 V on the MPC8245.
See Table 2 for details.
The MPC8245 PLL_CFG[0:4] setting 0x02 (0b00010) has a different ‘PCI-to-Mem’ and ‘Mem-to-CPU’
multiplier ratio than the same setting on the MPC8240, and thus, is not backwards-compatible. See Table 18
for details.
Most of the MPC8240 PLL_CFG[0:4] settings are subsets of the PCI_SYNC_IN input frequency range
accepted by the MPC8245. However, the parts will not be fully backwards-compatible since the ranges of
the two parts do not always match. Note that modes 0x8 and 0x18 of the MPC8245 are not compatible with
settings 0x8 and 0x18 on the MPC8240. See Table 18 and Table 19 for details.
There are two additional reset configuration signals on the MPC8245 which are not used as reset
configuration signals on the MPC8240: SDMA0 and SDMA1.
The SDMA0 reset configuration pin selects between the MPC8245 DUART or the MPC8240 backwards
compatible mode PCI_CLK[0:4] functionality on these multiplexed signals. The default state (logic 1) of
SDMA0 selects the MPC8240 backwards compatible mode of PCI_CLK[0:4] functionality while a logic 0
state on the SDMA0 signal selects DUART functionality. Note if using the DUART mode, four of the five
PCI clocks, PCI_CLK[0:3], are not available.
The SDMA1 reset configuration pin selects between MPC8245 extended ROM functionality or MPC8240
backwards-compatible functionality on the multiplexed signals: TBEN, CHKSTOP_IN, SRESET,
TRIG_IN, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240
backwards-compatible mode functionality, while a logic 0 state on the SDMA1 signal selects extended
ROM functionality. Note if using the extended ROM mode, TBEN, CHKSTOP_IN, SRESET, TRIG_IN,
and TRIG_OUT functionality are not available.
The driver names and capability of the pins for the MPC8245 and that of the MPC8240 vary slightly. Refer
to the Drive Capability table (for the ODCR register at 0x73) in the MPC8240 Integrated Processor
Hardware Specifications and Table 4 for more details.
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