参数资料
型号: MPC8266AZUPIBX
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480
封装: 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480
文件页数: 46/111页
文件大小: 1007K
代理商: MPC8266AZUPIBX
4
MPC826xA (HiP4) Family Hardware Specications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge (MPC8265A and MPC8266A only)
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
denable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for exible
support for communications protocols
相关PDF资料
PDF描述
MPC8264AZUMIBX 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480
MPC8264AZUPIBX 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480
MPC8265ACZUMHBC 32-BIT, 266 MHz, RISC PROCESSOR, PBGA480
MPC8260ACZUIHBX 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480
MPC8260AZUIHBX 32-BIT, 200 MHz, RISC PROCESSOR, PBGA480
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