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参数资料
| 型号： | MPC8266AZUPIBX |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA480 |
| 封装： | 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480 |
| 文件页数： | 68/111页 |
| 文件大小： | 1007K |
| 代理商： | MPC8266AZUPIBX |
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6
MPC826xA (HiP4) Family Hardware Specications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-dened TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
Additional features of the MPC826xA family are as follows:
CPM
— 32-Kbyte dual-port RAM
— Additional MCC host commands
— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
inverse multiplexing for ATM capabilities (IMA) (MPC8264A and MPC8266A only)
CPM multiplexing
— FCC2 can also be connected to the TC layer.
TC layer (MPC8264A and MPC8266A only)
— Each of the 8 TDM channels is routed in hardware to a TC layer block
– Protocol-specic overhead bits may be discarded or routed to other controllers by the SI
– Performing ATM TC layer functions (according to ITU-T I.432)
– Transmit (Tx) updates
– Cell HEC generation
– Payload scrambling using self synchronizing scrambler (programmable by the user)
– Coset generation (programmable by the user)
– Cell rate by inserting idle/unassigned cells
– Receive (Rx) updates
– Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
parameters for the delineation state machine
– Payload descrambling using self synchronizing scrambler (programmable by the user)
– Coset removing (programmable by the user)
– Filtering idle/unassigned cells (programmable by the user)
– Performing HEC error detection and single bit error correction (programmable by user)
– Generating loss of cell delineation status/interrupt (LOC/LCD)
— Operates with FCC2 (UTOPIA 8)
— Provides serial loop back mode
— Cell echo mode is provided
— Supports both FCC transmit modes
– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
The TC layer generates idle/unassigned cells to maintain the line bit rate.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8266AZUPJDC | 功能描述:微处理器 - MPU POWER QUICC II HIP4C RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8266CVR | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8266CZU | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8266VR | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
| MPC8266ZU | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC826xA (HiP4) Family Hardware Specifications |
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