参数资料
型号: MPC8308ZQAFD
厂商: Freescale Semiconductor
文件页数: 32/83页
文件大小: 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
标准包装: 84
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 473-LFBGA
供应商设备封装: 473-MAPBGA(19x19)
包装: 托盘
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
38
Freescale Semiconductor
PCI Express
Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications
11.4.3
Differential Receiver (RX) Input Specifications
This table defines the specifications for the differential input at all receivers (RXs). The parameters are
specified at the component pins.
Table 35. Differential Receiver (RX) Input Specifications
Parameter
Symbol
Comments
Min
Typical
Max
Units Note
Unit interval
UI
Each UPERX is 400 ps ± 300 ppm.
UPERX does not account for Spread
Spectrum Clock dictated variations.
399.88
400
400.12
ps
1
Differential peak-to-peak
output voltage
VRX-DIFFp-p
VPEDPPRX = 2*|VRX-D+ - VRX-D-|
0.175
1.200
V
2
Minimum receiver eye width
TRX-EYE
The maximum interconnect media and
Transmitter jitter that can be tolerated
by the Receiver can be derived as
TRX-MAX-JITTER = 1 - UPEEWRX= 0.6 UI.
0.4
UI
2, 3
Maximum time between the
jitter median and maximum
deviation from the median.
TRX-EYE-MEDIAN-to-
MAX-JITTER
Jitter is defined as the measurement
variation of the crossing points
(VPEDPPRX = 0 V) in relation to a
recovered TX UI. A recovered TX UI is
calculated over 3500 consecutive unit
intervals of sample data. Jitter is
measured using all edges of the 250
consecutive UI in the center of the 3500
UI used for calculating the TX UI.
——
0.3
UI
2, 3,
7
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
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