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参数资料
| 型号： | MPC8309VMAFDCA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA489 |
| 封装： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489 |
| 文件页数： | 63/81页 |
| 文件大小： | 484K |
| 代理商： | MPC8309VMAFDCA |
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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
66
Freescale Semiconductor
Clocking
23.1
Clocking in PCI Host Mode
When the MPC8309 is configured as a PCI host device (RCWH[PCIHOST] = 1), SYS_CLK_IN is its
primary input clock. SYS_CLK_IN feeds the PCI clock divider (
2) and the PCI_SYNC_OUT and
PCI_CLK multiplexors. The CFG_CLKIN_DIV configuration input selects whether SYS_CLK_IN or
SYS_CLK_IN/2 is driven out on the PCI_SYNC_OUT signal.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system.
23.1.1
PCI Clock Outputs (PCI_CLK[0:2])
When the MPC8309 is configured as a PCI host, it provides three separate clock output signals,
PCI_CLK[0:2], for external PCI agents.
When the device comes out of reset, the PCI clock outputs are disabled and are actively driven to a steady
low state. Each of the individual clock outputs can be enabled (enable toggling of the clock) by setting its
corresponding OCCR[PCICOEn] bit. All output clocks are phase-aligned to each other.
23.2
Clocking in PCI Agent Mode
When the MPC8309 is configured as a PCI agent device, PCI_SYNC_IN is the primary input clock. In
agent mode, the SYS_CLK_IN signal should be tied to GND, and the clock output signals, PCI_CLKn and
PCI_SYNC_OUT, are not used.
23.3
System Clock Domains
As shown in Figure , the primary clock input (frequency) is multiplied up by the system phase-locked loop
(PLL) and the clock unit to create four major clock domains:
The coherent system bus clock (csb_clk)
The QUICC Engine clock (qe_clk)
The internal clock for the DDR controller (ddr_clk)
The internal clock for the local bus controller (lbc_clk)
The csb_clk frequency is derived from the following equation:
csb_clk = [PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)] × SPMF
Eqn. 1
In PCI host mode,
PCI_SYNC_IN = SYS_CLK_IN
(1 + ~CFG_CLKIN_DIV) .
Eqn. 2
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset
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