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| 型号： | MPC8315VRAGDA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620 |
| 封装： | 29 X 29 MM, 2.23 MM HEIGHT, 1 MM PITCH, LEAD FREE, TEPBGAII-620 |
| 文件页数： | 28/112页 |
| 文件大小： | 1283K |
| 代理商： | MPC8315VRAGDA |
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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 0
22
Freescale Semiconductor
DDR and DDR2 SDRAM
7.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time at MCK[n]/MCK[n] crossing
tMCK
7.5
10
ns
2
ADDR/CMD output setup with respect to MCK
266 MHz
200 MHz
tDDKHAS
2.9
3.5
—
ns
3
ADDR/CMD output hold with respect to MCK
266 MHz
200 MHz
tDDKHAX
3.15
4.20
—
ns
3
MCS[n] output setup with respect to MCK
266 MHz
200 MHz
tDDKHCS
3.15
4.20
—
ns
3
MCS[n] output hold with respect to MCK
266 MHz
200 MHz
tDDKHCX
3.15
4.20
—
ns
3
MCK to MDQS Skew
tDDKHMH
–0.6
0.6
ns
4
MDQ//MDM output setup with respect to MDQS
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
900
1000
—
ps
5
MDQ//MDM output hold with respect to MDQS
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
1100
1200
—
ps
5
MDQS preamble start
tDDKHMP
–0.5
× tMCK – 0.6 –0.5 × tMCK + 0.6
ns
6
MDQS epilogue end
tDDKHME
–0.6
0.6
ns
6
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust
in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the
same adjustment value. See the
MPC8315E PowerQUICC II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (),
or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
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