参数资料
型号: MPC8343CVRADDX
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件页数: 65/92页
文件大小: 987K
代理商: MPC8343CVRADDX
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
68
Freescale Semiconductor
Clocking
As shown in Figure 33, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)
which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,
Clocking, and Initialization,” in the MPC8349E Reference Manual for more information on the clock
subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWL[DDRCM]
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(
÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk = csb_clk × (1 + RCWL[LBIUCM]
Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the a LBIU clock divider
to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider
ratio is controlled by LCCR[CLKDIV].
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 45 specifies which units have a configurable clock
frequency.
Table 45. Configurable Clock Units
Unit
Default
Frequency
Options
TSEC2, I2C1
csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
Security Core
csb_clk/3
Off,
csb_clk, csb_clk/2, csb_clk/3
PCI and DMA complex
csb_clk
Off,
csb_clk
相关PDF资料
PDF描述
MPC8343ZQAGDX 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
MPC8343EZQAGDX 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
MPC8343ECVRADDX 32-BIT, 266 MHz, MICROPROCESSOR, PBGA620
MPC8343CVRAGDX 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
MPC8343CZQAGDX 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
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