参数资料
型号: MPC8378CVRALG
厂商: Freescale Semiconductor
文件页数: 36/128页
文件大小: 0K
描述: MPU POWERQUICC II PRO 689-PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
15
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the chip.
5.1
RESET DC Electrical Characteristics
This table provides the DC electrical characteristics for the RESET pins of the device.
5.2
RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications of the device.
Table 10. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.0
OVDD + 0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
——
± 30
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Notes:
This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.
HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET to activate reset flow
32
tPCI_SYNC_IN
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
32
tCLKIN
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32
tPCI_SYNC_IN
HRESET assertion (output)
512
tPCI_SYNC_IN
HRESET negation to negation (output)
16
tPCI_SYNC_IN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
4—
tCLKIN
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4—
tPCI_SYNC_IN
Input hold time for POR config signals with respect to negation of HRESET
0—
ns
相关PDF资料
PDF描述
355-020-520-204 CARDEDGE 20POS DL .156 LOPRO BLK
MPC8378CVRAJF MPU POWERQUICC II PRO 689-PBGA
MPC8378CVRAGD MPU POWERQUICC II PRO 689-PBGA
MC8640DHX1067NC MPU DUAL E600 1023-FCCBGA
345-012-527-202 CARDEDGE 12POS DUAL .100 GREEN
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