参数资料
型号: MPC8378CVRALG
厂商: Freescale Semiconductor
文件页数: 97/128页
文件大小: 0K
描述: MPU POWERQUICC II PRO 689-PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
70
Freescale Semiconductor
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
It is recommended that the recovered Tx UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
Figure 46. Minimum Transmitter Timing and Voltage Output Compliance Specifications
15.4.3
Differential Receiver (Rx) Input Specifications
This table defines the specifications for the differential input at all receivers. The parameters are specified
at the component pins.
Table 58. Differential Receiver (Rx) Input Specifications
Parameter
Comments
Symbol
Min
Typical
Max
Units
Note
Unit interval
Each UPERX is 400 ps ± 300
ppm. UPERX does not account
for Spread Spectrum Clock
dictated variations.
UI
399.88
400
400.12
ps
Differential peak-to-peak
output voltage
VPEDPPRX = 2 × |VRX-D+
VRX-D-|
VRX-DIFFp-p
0.175
1.200
V
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
相关PDF资料
PDF描述
355-020-520-204 CARDEDGE 20POS DL .156 LOPRO BLK
MPC8378CVRAJF MPU POWERQUICC II PRO 689-PBGA
MPC8378CVRAGD MPU POWERQUICC II PRO 689-PBGA
MC8640DHX1067NC MPU DUAL E600 1023-FCCBGA
345-012-527-202 CARDEDGE 12POS DUAL .100 GREEN
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