参数资料
型号: MPC8378CVRALG
厂商: Freescale Semiconductor
文件页数: 61/128页
文件大小: 0K
描述: MPU POWERQUICC II PRO 689-PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
38
Freescale Semiconductor
This figure shows the MII management AC timing diagram.
Figure 20. MII Management Interface Timing Diagram
9USB
This section provides the AC and DC electrical characteristics for the USB dual-role controllers.
MDC rise time (20%–80%)
tMDCR
——
10
ns
MDC fall time (80%–20%)
tMDCF
——
10
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed.
3. Guaranteed by design.
4. tplb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].
Table 38. MII Management AC Timing Specifications (continued)
Parameter
Symbol1
Min
Typical
Max
Unit
Note
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
相关PDF资料
PDF描述
355-020-520-204 CARDEDGE 20POS DL .156 LOPRO BLK
MPC8378CVRAJF MPU POWERQUICC II PRO 689-PBGA
MPC8378CVRAGD MPU POWERQUICC II PRO 689-PBGA
MC8640DHX1067NC MPU DUAL E600 1023-FCCBGA
345-012-527-202 CARDEDGE 12POS DUAL .100 GREEN
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