参数资料
型号: MPC8378CVRALG
厂商: Freescale Semiconductor
文件页数: 49/128页
文件大小: 0K
描述: MPU POWERQUICC II PRO 689-PBGA
标准包装: 27
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
27
Figure 8. SGMII Transmitter DC Measurement Circuit
8.2.3
DC Requirements for SGMII SD_REF_CLK and SD_REF_CLK_B
8.3
SGMII, MII, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for SGMII, MII, RGMII, RMII, and RTBI are presented in this section.
Input differential voltage
SEIC
x = 01
SEIC
x = 00
VRX_DIFFp-p
100
175
—1200
mV
Loss of signal threshold
SEIC
x = 01
SEIC
x = 00
VLOS
30
65
100
175
mV
Input AC common mode voltage
VCM_ACp-p
100
mV
Receiver differential input
impedance
ZRX_DIFF
80
100
120
Ω
Receiver common mode input
impedance
ZRX_CM
20
35
Ω
Common mode input voltage
VCM
—Vxcorevss
—V
Notes:
1. Input must be externally AC-coupled.
2. VRX_DIFFp-p is also referred to as peak to peak input differential voltage.
3. The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in PCI Express. Refer to PCI
Express Differential Receiver (RX) Input Specifications section for further explanation.
4. The SEIC
x shown in the table refers to SRDSnCR[SEICA] for lane A and SRDSnCR[SEICE] for lane E.
5. VCM_ACp-p is also referred to as peak to peak AC common mode voltage.
6. On-chip termination to SGND_SRDS
n (xcorevss).
Table 27. SGMII DC Receiver Electrical Characteristics (continued)
Parameter
Symbol
Min
Typical
Max
Unit
Note
50
Ω
Transmitter
L1_SD_TX
n
L1_SD_TX
n
50
Ω
Vos
VOD
MPC8378E SGMII
SerDes Interface
50
Ω
50
Ω
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