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| 型号： | MPC8544DVTANG |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783 |
| 封装： | 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783 |
| 文件页数： | 127/128页 |
| 文件大小： | 1411K |
| 代理商： | MPC8544DVTANG |
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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
98
Freescale Semiconductor
Package Description
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 K
Ω) be placed on this pin to OVDD.
3. This pin must always be pulled high.
4. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pull-up or active driver is needed. TSEC3_TXD[3] (cfg_srds_sgmii_refclk) is an exception, because the
default value of this configuration signal is low (0). Thus, no external pull-down resistor is needed for selecting the default
configuration value.
5. Treat these pins as no connects (NC) unless using debug address functionality.
6. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ω pull-up or pull-down
resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.”
7. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-k
Ω
pull-up or pull-down resistors. See Section 19.3, “e500 Core PLL Ratio.”
8. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. Therefore, this pin will be described as an I/O for boundary scan.
9. For proper state of these signals during reset, DMA_DACK[1] must be pulled down to GND through a resistor.
DMA_DACK[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down
the value of the net at reset, then a pullup is needed on DMA_DACK[0].
10. This output is actively driven during reset rather than being three-stated during reset.
11. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
12. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
13. Anode and cathode of internal thermal diode.
14. Treat pins AC7, T5, V2, and M7 as spare configuration pins cfg_spare[0:3]. The spare pins are unused POR config pins. It
is highly recommended that the customer provide the capability of setting these pins low (that is, pull-down resistor which
is not currently stuffed) in order to support new config options should they arise between revisions.
15. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
during reset.
16. This pin is only an output in FIFO mode when used as Rx flow control.
17. Do not connect.
18. These are test signals for factory use only and must be pulled up (100
Ω to 1 kΩ) to OVDD for normal machine operation.
19. Independent supplies derived from board VDD.
20. Recommend a pull-up resistor (1 K~) be placed on this pin to OVDD.
21. The following pins must not be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE,
MSRCID[2:4], and ASLEEP.
22. This pin requires an external 4.7-k
Ω pull-down resistor to prevent PHY from seeing a valid transmit enable before it is
actively driven.
23. General-purpose POR configuration of user system.
Table 63. MPC8544EPinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
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相关代理商/技术参数 |
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| MPC8544DVTANGA | 功能描述:数字信号处理器和控制器 - DSP, DSC PQ38K 8544 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MPC8544EAVTALF | 功能描述:微处理器 - MPU PQ3 8544E Netwrk Comm Indstrl Cntrl RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8544EAVTALFA | 功能描述:数字信号处理器和控制器 - DSP, DSC PQ38K 8544E RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| MPC8544EAVTANG | 功能描述:微处理器 - MPU PQ3 8544E Netwrk Comm Indstrl Cntrl RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8544EAVTANGA | 功能描述:数字信号处理器和控制器 - DSP, DSC PQ38K 8544E RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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