参数资料
型号: MPC8544DVTANG
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件页数: 74/128页
文件大小: 1411K
代理商: MPC8544DVTANG
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
5
MPC8544E Overview
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the I2C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I2C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data bus operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
— Two protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
— Parity support
— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Two enhanced three-speed Ethernet controllers (eTSECs)
— Three-speed support (10/100/1000 Mbps)
— Two IEEE Standard 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, and 802.3ab compliant
controllers
— Support for various Ethernet physical interfaces:
– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, SGMII, and RGMII.
– 10/100 Mbps full- and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII.
— Flexible configuration for multiple PHY interface configurations.
— TCP/IP acceleration and QoS features available
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
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