参数资料
型号: MPC8569EVTAUNL
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: RISC PROCESSOR, PBGA783
封装: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件页数: 109/126页
文件大小: 2847K
代理商: MPC8569EVTAUNL
High-Speed SerDes Interfaces (HSSI)
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
83
Figure 43. Differential Measurement Points for Rise and Fall Time
Figure 44. Single-Ended Measurement Points for Rise and Fall Time Matching
Differential input high voltage
VIH
200
mV
4
Differential input low voltage
VIL
–200
mV
4
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-Fall
Matching
——
20
%
5, 6, 7
Notes:
1. Caution: Only 100 and 125 have been tested. In-between values will not work correctly with the rest of the system.
2. Limits from PCI Express CEM Rev 2.0
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLK minus SD_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 43.
4. Measurement taken from differential waveform
5. Measurement taken from single-ended waveform
6. Matching applies to rising edge for SD_REF_CLK and falling edge rate for SD_REF_CLK. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLK rising meets SD_REF_CLK falling. The median cross point
is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of
SD_REF_CLK must be compared to the fall edge rate of SD_REF_CLK, the maximum allowed difference should not exceed
20% of the slowest edge rate. See Figure 44.
7. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing
Table 47. SD_REF_CLK and SD_REF_CLK Input Clock Requirements (continued)
At recommended operating conditions with ScoreVDD = 1.0 V ± 3%. and 1.1 V ± 3%
Parameter
Symbol
Min
Typ
Max
Unit
Notes
VIH = +200 mV
VIL = –200 mV
0.0 V
SD_REF_CLK
SD_REF_CLK
Fall Edge Rate
Rise Edge Rate
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