参数资料
型号: MPC870ZT80
厂商: 飞思卡尔半导体(中国)有限公司
英文描述: Hardware Specifications
中文描述: 硬件规格
文件页数: 7/84页
文件大小: 1366K
代理商: MPC870ZT80
MPC875/MPC870 Hardware Specifications, Rev. 3.0
15
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Layout Practices
10 Layout Practices
Each VDD pin on the MPC875/870 should be provided with a low-impedance path to the board’s supply. Each GND
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The VDD power supply should be bypassed to ground using at least four 0.1-F bypass capacitors
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed
circuit traces connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. At a
minimum, a four-layer board employing two inner layers as VDD and GND planes should be used.
All output pins on the MPC875/870 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches
are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to
the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the VDD and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to Section 14.4.3, “Clock Synthesizer Power (VDDSYN,
VSSSYN, VSSSYN1),” of the MPC885 PowerQUICC Family User’s Manual.
11 Bus Signal Timing
The maximum bus speed supported by the MPC875/870 is 80 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC875/870 used at 133 MHz must be configured for a 66 MHz bus). Table 8
shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 9 shows the frequency ranges
for standard part frequencies in 2:1 bus mode.
PCDIR
(Port C data direction register)
PCDIR[4:5]
PCDIR[8:9]
PCDIR[14]
0
PDPAR
(Port D pin assignment register)
PDPAR[3:7]
PDPAR[9:5]
0
PDDIR
(Port D data direction register)
PDDIR[3:7]
PDDIR[9:15]
0
Table 8. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Frequency
66 MHz
80 MHz
Min
Max
Min
Max
Core frequency
40
66.67
40
80
Bus frequency
40
66.67
40
80
Table 7. Mandatory Reset Configuration of MPC875/870 (continued)
Register/Configuration
Field
Value
(binary)
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相关代理商/技术参数
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MPC870ZTZZ 制造商:Freescale Semiconductor 功能描述:
MPC875CVR133 功能描述:微处理器 - MPU 133 MHz 176 MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC875CVR66 功能描述:微处理器 - MPU 66 MHz 87 MIPS RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC875CZT133 功能描述:微处理器 - MPU PQ I HIP6W DUET RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC875CZT66 功能描述:微处理器 - MPU PQ I HIP6W DUET RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324