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参数资料
| 型号： | MPC92459FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 6/10页 |
| 文件大小： | 376K |
| 代理商： | MPC92459FA |
MPC92459
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
457
Table 6. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)1
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (fREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:6], N[0:1], OE)
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.8
V
LVCMOS
IIN
Input Current2
±200
A
VIN = VCC or GND
Differential Clock Output fOUT
VPP
Output Differential Voltage (peak-to-peak)
250
mV
LVDS
VOS
Output Offset Voltage
1125
1275
mV
LVDS
Test and Diagnosis Output TEST
VOH
Output High Voltage
2.0
V
IOH =–0.8 mA
VOL
Output Low Voltage
0.55
V
IOL = 0.8 mA
Supply Current
ICC_PLL Maximum PLL Supply Current
20
mA
VCC_PLL Pins
ICC
Maximum Supply Current
110
mA
All VCC Pins
1. All AC characteristics are design targets and subject to change upon device characterization.
2. Inputs have pull-down resistors affecting the input current.
Table 7. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)1
1. All AC characteristics are design targets and subject to change upon device characterization.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal Interface Frequency Range
10
20
MHz
fVCO
VCO Frequency Range2
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL 2 M.
800
1800
MHz
fMAX
Output Frequency
N = 11 (
÷ 1)
N = 00 (
÷ 2)
N = 01 (
÷ 4)
N = 10 (
÷ 8)
400
200
100
50
900
450
225
112.5
MHz
PWR_DOWN = 0
fS_CLOCK Serial Interface Programming Clock Frequency3
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as
test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
0
10
MHz
tP,MIN
Minimum Pulse Width
(S_LOAD, P_LOAD)
50
ns
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.05
TBD
ns
20% to 80%
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
tJIT(CC)
Cycle-to-Cycle Jitter
RMS (1
σ)4
4. Refer to the application section for a jitter calculation for other confidence factors than 1
σ.
TBD
ps
tJIT(PER)
Period Jitter
RMS (1
σ)
±25
ps
tLOCK
Maximum PLL Lock Time
10
ms
MPC92459
900 MHz Low Voltage LVDS Clock Synthesizer
NETCOM
IDT 900 MHz Low Voltage LVDS Clock Synthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC92459
5
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