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参数资料
| 型号： | MPC930FA |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封装： | TQFP-32 |
| 文件页数： | 11/14页 |
| 文件大小： | 544K |
| 代理商： | MPC930FA |
MPC930 MPC931
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 3
6
APPLICATIONS INFORMATION
Programming the MPC930/931
The MPC930/931 clock driver outputs can be configured
into several frequency relationships, in addition the external
feedback option allows for a great deal of flexibility in
establishing unique input to output frequency relationships.
The output dividers for the three output groups allows the
user to configure the outputs into 1:1, 2:1, 3:1, 3:2 and 3:2:1
frequency ratios. The use of even dividers ensures that the
output duty cycle is always 50%. Table 1 illustrates the
various output configurations, the table describes the outputs
using the VCO frequency as a reference. As an example for a
3:2:1 relationship the Qa outputs would be set at VCO/2, the
Qb’s at VCO/4 and the Qc’s at VCO/6. These settings will
provide output frequencies with a 3:2:1 relationship.
The division settings establish the output relationship, but
one must still ensure that the VCO will be stable given the
frequency of the outputs desired. The VCO lock range can be
found in the specification tables. The feedback frequency
and the Power_Dn pin can be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL is such that for output frequencies between 25 and
180MHz the MPC930/931 can generally be configured into a
stable region.
The relationship between the input reference and the
output frequency is also very flexible. Table 2 shows the
multiplication factors between the inputs and outputs when
the internal feedback option is used. For external feedback
Table 1 can be used to determine the multiplication factor,
there are too many potential combinations to tabularize the
external feedback condition. Figure 5 through Figure 10
illustrates several programming possibilities, although not
exhaustive it is representative of the potential applications.
Table 1. Programmable Output Frequency Relationships
(Power_Dn = ‘0’)
INPUTS
OUTPUTS
Div_Sela
Div_Selb
Div_Selc
Qa
Qb
Qc
0
VCO/2
VCO/4
0
1
VCO/2
VCO/6
0
1
0
VCO/2
VCO/4
0
1
VCO/2
VCO/4
VCO/6
1
0
VCO/4
VCO/2
VCO/4
1
0
1
VCO/4
VCO/2
VCO/6
1
0
VCO/4
1
VCO/4
VCO/6
Table 2. Input Reference/Output Frequency Relationships (Internal Feedback Only)
INPUTS
OUTPUTS
Qa
Qb
Qc
Div_Sela
Div_Selb
Div_Selc
Power_Dn=0
Power_Dn=1
Power_Dn=0
Power_Dn=1
Power_Dn=0
Power_Dn=1
0
4x
2x
4x
2x
x
0
1
4x
2x
4x
2x
4/3x
2/3x
0
1
0
4x
2x
x
2x
x
0
1
4x
2x
x
4/3x
2/3x
1
0
2x
x
4x
2x
x
1
0
1
2x
x
4x
2x
4/3x
2/3x
1
0
2x
x
2x
x
2x
x
1
2x
x
2x
x
4/3x
2/3x
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MPC930 MPC931
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC930 MPC931
6
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相关代理商/技术参数 |
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| MPC931 | 制造商:Motorola Inc 功能描述: |
| MPC9315 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:2.5V and 3.3V CMOS PLL Clock Generator and Driver |
| MPC9315AC | 功能描述:锁相环 - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| MPC9315ACR2 | 功能描述:时钟发生器及支持产品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| MPC9315FA | 功能描述:锁相环 - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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