参数资料
型号: MPC930FA
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32
封装: TQFP-32
文件页数: 7/14页
文件大小: 544K
代理商: MPC930FA
MPC930 MPC931
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 3
2
÷2
÷4
÷2
÷4
÷6
FUNCTION TABLES
TCLK_Sel
Reference
0
1
xtal (PECL_CLK)
TCLK
PLL_En
PLL Status
0
1
Test Mode
PLL Enabled
ExtFB_Sel
Reference
0
1
Int.
÷8
Ext_FB
GNDO
Qa1
Qa0
VCCO
Div_Sela
Div_Selb
Div_Selc
NC
GNDO
Qc1
Qc0
VCCO
Ext_FB
Shut_Dn1
Shut_Dn0
NC
GNDO
Qb0
Qb1
VCCO
ExtFB_Sel
TCLK_Sel
PLL_En
NC
PLL_VCC
Power_Dn
TCLK
MR/T
ristate
xtal1
(930)
xtal2
(930)
GNDI
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12
345678
24
23
22
21
20
19
18
17
16
MPC930/
MPC931
Power_Dn
PLL Status
0
1
VCO/1
VCO/2
Div_Sela,b,c
0
1
Qa
Qb
Qc
Shut_Dn1
0
1
Div_Seln
Qb & Qc Low, Qa Toggle
Qa & Qb Low, Qc Toggle
Qb Low, Qa & Qc Toggle
All Toggle
Shut_Dn0
0
1
0
1
Figure 1. 32–Lead Pinout (Top View)
PECL_CLK
(931)
PECL_CLK
(931)
Figure 2. Logic Diagram
POWER–ON RESET
VCO
PHASE
DETECTOR
LPF
÷8
MR/Tristate
xtal
OSC
Shut_Dn1
Shut_Dn0
xtal2
xtal1
PLL_En
Qa0
Qb0
Qb1
Power_Dn
÷2/÷4
÷4/÷6
Qc0
Qc1
DISABLE
LOGIC
Div_Selb
Div_Sela
Qa1
TCLK
TCLK_Sel
Ext_FB
ExtFB_Sel
Div_Selc
MPC930
PECL_CLK
MPC931
MR/Tristate
PLL Status
0
1
Disabled
Enabled
(Pullup)
(Pulldown)
(Pullup)
(Pulldown)
(Pullup)
(Pulldown)
(Pullup)
(None)
÷2
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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c
..
.
MPC930 MPC931
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC930 MPC931
2
相关PDF资料
PDF描述
MPC930FA 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32
MPC972FA 125 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52
MPC9850VF 500 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100
MPC9850VMR2 500 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100
MPC9850VMR2 500 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100
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