参数资料
型号: MPC930FA
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32
封装: TQFP-32
文件页数: 4/14页
文件大小: 544K
代理商: MPC930FA
MPC930 MPC931
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 3
12
Figure 17. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 18 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 18. Optimized Dual Line Termination
7
MPC930/931
OUTPUT
BUFFER
RS = 36
ZO = 50
RS = 36
ZO = 50
7
+ 36 k 36 = 50 k 50
25
= 25
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MPC930 MPC931
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC930 MPC931
12
相关PDF资料
PDF描述
MPC930FA 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32
MPC972FA 125 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52
MPC9850VF 500 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100
MPC9850VMR2 500 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100
MPC9850VMR2 500 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA100
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