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参数资料
| 型号： | MPC9330FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 120 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 10/10页 |
| 文件大小： | 148K |
| 代理商： | MPC9330FA |
MPC9330
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
86
RS = 36 || 36
R0 = 14
VL = 3.0 ( 25 ÷ (18+14+25)
= 1.31V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.6V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
1. Final skew data pending specification.
Figure 5. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 6 “Optimized Dual Line Termination” should be used.
In this case the series terminating resistors are reduced such
that when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
Figure 6. Optimized Dual Line Termination
14
MPC9330
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 k 22 = 50 k 50
25
= 25
Figure 7. CCLK MPC9330 AC test reference for Vcc = 3.3V
Pulse
Generator
Z = 50W
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9330 DUT
VTT
2
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