
MPC9330
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
84
Table 10: MPC9330 Example Configurations (Internal Feedback: FB_SEL = 0)
frefa [MHz]
PWR_DN
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
0
fref
4 (50-120 MHz)
fref
4 (50-120 MHz)
fref
2
(25–60 MHz)
0
1
fref
4 (50-120 MHz)
fref
4 (50-120 MHz)
fref
4÷3 (16.6–40 MHz)
0
1
0
fref
4 (50-120 MHz)
fref
2 (25–60 MHz)
fref
2
(25–60 MHz)
0
1
fref
4 (50-120 MHz)
fref
2 (25–60 MHz)
fref
4÷3 (16.6–40 MHz)
0
1
0
fref
2 (25–60 MHz)
fref
4 (50-120 MHz)
fref
2
(25–60 MHz)
0
1
0
1
fref
2 (25–60 MHz)
fref
4 (50-120 MHz)
fref
4÷3 (16.6–40 MHz)
0
1
0
fref
2 (25–60 MHz)
fref
2 (25–60 MHz)
fref
2
(25–60 MHz)
0
1
fref
2 (25–60 MHz)
fref
2 (25–60 MHz)
fref
4÷3 (16.6–40 MHz)
12.5-30.0
1
0
fref
2 (25–60 MHz)
fref
2 (25–60 MHz)
fref
(12.5–30 MHz)
12.530.0
1
0
1
fref
2 (25–60 MHz)
fref
2 (25–60 MHz)
fref
2÷3 (8.33–20 MHz)
1
0
1
0
fref
2 (25–60 MHz)
fref
(12.5–30 MHz)
fref
(12.5–30 MHz)
1
0
1
fref
2 (25–60 MHz)
fref
(12.5–30 MHz)
fref
2÷3 (8.33–20 MHz)
1
0
fref
(12.5–30 MHz)
fref
2 (25–60 MHz)
fref
(12.5–30 MHz)
1
0
1
fref
(12.5–30 MHz)
fref
2 (25–60 MHz)
fref
2÷3 (8.33–20 MHz)
1
0
fref
(12.5–30 MHz)
fref
(12.5–30 MHz)
fref
(12.5–30 MHz)
1
fref
(12.5–30 MHz)
fref
(12.5–30 MHz)
fref
2÷3 (8.33–20 MHz)
a. fref is the input clock reference frequency (CCLK or XTAL)
Table 11: MPC9330 Example Configurations (External Feedback and PWR_DN = 0)
PLL
Feedback
frefa
[MHz]
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
0
fref (50-120 MHz)
fref
(50-120 MHz)
fref
÷2
(25–60 MHz)
VCO
÷ 4b
50-120
0
1
fref (50-120 MHz)
fref
(50-120 MHz)
fref
÷3
(16.6–40 MHz)
VCO
÷ 4b
50-120
0
1
0
fref (50-120 MHz)
fref
÷2
(25–60 MHz)
fref
÷2
(25–60 MHz)
0
1
fref (50-120 MHz)
fref
÷2
(25–60 MHz)
fref
÷3
(16.6–40 MHz)
1
0
fref (25–60 MHz)
fref
2
(50-120 MHz)
fref
(25–60 MHz)
VCO
÷ 8c
25-60
1
0
1
fref (25–60 MHz)
fref
2
(50-120 MHz)
fref 2
÷3 (16.6–40 MHz)
VCO
÷ 8c
25-60
1
0
fref (25–60 MHz)
fref
(25–60 MHz)
fref
(25–60 MHz)
1
fref (25–60 MHz)
fref
(25–60 MHz)
fref 2
÷3 (16.6–40 MHz)
0
1
fref
3 (50-120 MHz)
fref
3 (50-120 MHz)
fref
(16.6–40 MHz)
VCO
÷ 12d
16 67-40
0
1
fref
3 (50-120 MHz)
fref
3÷2 (25–60 MHz)
fref
(16.6–40 MHz)
VCO
÷ 12d
16.67-40
1
0
1
fref
3÷2 (25–60 MHz)
fref
3 (50-120 MHz)
fref
(16.6–40 MHz)
1
fref
3÷2 (25–60 MHz)
fref
3÷2 (25–60 MHz)
fref
(16.6–40 MHz)
a. fref is the input clock reference frequency (CCLK or XTAL)
b. QAx connected to FB_IN and FSELA=0, PWR_DN=0
c. QAx connected to FB_IN and FSELA=1, PWR_DN=0
d. QCx connected to FB_IN and FSELC=1, PWR_DN=0
Table 12: MPC9330 Example Configurations (External Feedback and PWR_DN = 1)
PLL
Feedback
frefa [MHz]
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
1
0
fref
(12.5–30 MHz)
fref 2
(25–60 MHz)
fref
(12.5–30 MHz)
VCO
÷ 16b
12 5–30
1
0
1
fref
(12.5–30 MHz)
fref 2
(25–60 MHz)
fref 2
÷3 (8.33–20 MHz)
VCO
÷ 16b
12.5–30
1
0
fref
(12.5–30 MHz)
fref
(12.5–30 MHz)
fref
(12.5–30 MHz)
1
fref
(12.5–30 MHz)
fref
(12.5–30 MHz)
fref 2
÷3 (8.33–20 MHz)
0
1
fref 3
(25–60 MHz)
fref 3
(25–60 MHz)
fref
(8.33–20 MHz)
VCO
÷ 24c
8 33–20
0
1
fref 3
(25–60 MHz)
fref 3
÷2 (12.5–30 MHz)
fref
(8.33–20 MHz)
VCO
÷ 24c
8.33–20
1
0
1
fref 3
÷2 (12.5–30 MHz)
fref 3
(25–60 MHz)
fref
(8.33–20 MHz)
1
fref 3
÷2 (12.5–30 MHz)
fref 3
÷2 (12.5–30 MHz)
fref
(8.33–20 MHz)
a. fref is the input clock reference frequency (CCLK or XTAL)
b. QAx connected to FB_IN and FSELA=1, PWR_DN=1
c. QCx connected to FB_IN and FSELC=1, PWR_DN=1
2