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参数资料
| 型号： | MPC9330FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 120 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 6/10页 |
| 文件大小： | 148K |
| 代理商： | MPC9330FA |
MPC9330
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
82
Table 7: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Reference Frequencyb
÷ 4 feedbackc
PLL mode, external feedback
÷ 8 feedback
÷ 12 feedback
÷ 16 feedback
÷ 24 feedback
PLL mode, internal feedback
÷ 16 feedback)
Input Reference Frequency in PLL bypass moded
50
25
16.67
12.5
8.33
12.5
120
60
40
30
20
30
TBD
MHz
PLL locked
fVCO
VCO Lock Frequency Rangee
200
480
MHz
fXTAL
Crystal Interface Frequency Rangef
10
25
MHz
fMAX
Output Frequency
÷ 4 output
÷ 8 output
÷ 12 output
÷ 16 output
÷ 24 output
50
25
16.67
12.5
8.33
120
60
40
30
20
MHz
PLL locked
frefDC
tPW, MIN
Reference Input Duty Cycle
Minimum Input Reference Pulse Width
25
2
75
%
ns
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0V
t()
Propagation Delay (SPO)g for the
– entire fref range
– fref = 8.33 MHz
– fref = 50.0 MHz
–1.2
–400
–70
+1.2
+400
+70
°
ps
tsk(o)
Output-to-Output Skewh
(within output bank)
(any output)
50
150
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
50
300
ps
tJIT(PER)
Period Jitter
35
250
ps
tJIT()
I/O Phase Jitter
RMS (1
s)
10
70
ps
BW
PLL closed loop bandwidthi
÷ 4 feedback
PLL mode, external feedback
÷ 8 feedback
÷ 12 feedback
÷ 16 feedback
÷ 24 feedback
0.8–5.0
0.5–2.0
0.3–1.0
0.25–0.6
0.2–0.5
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a. AC characteristics apply for parallel output termination of 50
to VTT.
b. PLL mode requires PLL_EN = 0 to enable the PLL.
c.
÷4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one ÷2 output to FB_IN. See Table 1 to Table 3 for
other feedback configurations.
d. In bypass mode, the MPC9330 divides the input reference clock.
e. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
f.
The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
g. SPO is the static phase offset between CCLK and FB_IN (FB_SEL=1 and PLL locked). tsk(o) [ps] = tsk(o) [°] B(fref 360°)
h. Skew data applicable for equally loaded outputs only.
i.
–3 dB point of PLL transfer characteristics.
2
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